TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 294

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.4
Control Registers in the I2C Bus Mode
11.4.2
31-8
7-5
4
3
2-1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
-
BC[2:0]
ACK
-
SCK[2:1]
SCK[0]
SWRMON
Bit Symbol
SBIxCR1(Control register 1)
31
23
15
0
0
0
7
0
-
-
-
R
R/W
R/W
R
R/W
W
R
Type
BC
30
22
14
0
0
0
6
0
-
-
-
Read as 0.
Select the number of bits per transfer (Note 1)
Master mode
0: Acknowledgement clock pulse is not generated.
1: Acknowledgement clock pulse is generated.
Slave mode
0: Acknowledgement clock pulse is not counted.
1: Acknowledgement clock pulse is counted.
Read as 1.
Select internal SCL output clock frequency (Note 2).
On reading <SWRMON>: Software reset status monitor
0:Software reset operation is in progress.
1:Software reset operation is not in progress.
<BC>
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
29
21
13
0
0
0
5
0
-
-
-
clock cycles
Number of
n = 10
n = 11
n = 5
n = 6
n = 7
n = 8
n = 9
When <ACK> = 0
8
1
2
3
4
5
6
7
Page 274
ACK
28
20
12
0
0
0
4
0
-
-
-
reserved
385 kHz
294 kHz
200 kHz
122 kHz
68 kHz
36 kHz
19 kHz
length
Data
8
1
2
3
4
5
6
7
27
19
11
Function
0
0
0
3
1
-
-
-
-
clock cycles
Number of
When <ACK> = 1
9
2
3
4
5
6
7
8
System Clock: fsys
Clock gear : fc/1
Frequency =
SCK2
26
18
10
0
0
0
2
0
-
-
-
length
Data
TMPM333FDFG/FYFG/FWFG
8
1
2
3
4
5
6
7
2
n
fsys
+ 72
( = 40 MHz)
[Hz]
SCK1
25
17
0
0
9
0
1
0
-
-
-
SWRMON
1(Note3)
SCK0 /
24
16
0
0
8
0
0
-
-
-