TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 430

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15.3
On-board Programming of Flash Memory (Rewrite/Erase)
(2)
the next address of the address specified in the fourth bus write cycle (in the fourth bus write cycle, the
page top address will be command written) (32 bits of data is input at a time). Be sure to use the 32-bit
data transfer command in writing commands on and after the fourth bus cycle. In this, any 32-bit data
transfer commands shall not be placed across word boundary. On and after the fifth bus write cycle,
data is command written to the same page area. Even if it is desired to write the page only partially, it
is required to perform the automatic page programming for the entire page. In this case, the address
input for the fourth bus write cycle shall be set to the top address of the page. Be sure to perform command
write operation with the input data set to "1" for the data cells not to be set to "0." For example, if the
top address of a page is not to be written, set the input data of the fourth bus write cycle to 0xFFFFFFFF
to command write the data.
can be checked by monitoring FCFLCS<RDY/BSY>. Any new command sequence is not accepted
while it is in automatic page programming mode. If it is desired to stop operation, use the hardware reset
function. Be careful in doing so because data cannot be written normally if the operation is interrupted.
When a single page has been command written normally terminating the automatic page writing process,
FCFLCS<RDY/BSY> is set to "1" and it returns to the read mode.
for each page because the number of pages to be written by a single execution of the automatic page
program command is limited to only one page. It is not allowed for automatic page programming to
process input data across pages.
returns to the read mode. This condition can be checked by monitoring FCFLCS<RDY/BSY> . If au-
tomatic programming has failed, the flash memory is locked in the mode and will not return to the read
mode. For returning to the read mode, it is necessary to execute hardware reset to reset the flash memory
or the device. In this case, while writing to the address has failed, it is recommended not to use the device
or not to use the block that includes the failed address.
completed.
operation is performed internally to the device, be sure to read the data to confirm that data has been
correctly erased. Any new command sequence is not accepted while it is in an automatic chip erase
operation. If it is desired to stop operation, use the hardware reset function. If the operation is forced to
stop, it is necessary to perform the automatic chip erase operation again because the data erasing oper-
ation has not been normally terminated.
operation will not be performed and it returns to the read mode after completing the sixth bus read cycle
of the command sequence. When an automatic chip erase operation is normally terminated, it automat-
ically returns to the read mode. If an automatic chip erase operation has failed, the flash memory is
locked in the mode and will not return to the read mode.
case, the failed block cannot be detected. It is recommended not to use the device anymore or to identify
the failed block by using the block erase function for not to use the identified block anymore.
Once the third bus cycle is executed, the automatic page programming is in operation. This condition
When multiple pages are to be written, it is necessary to execute the page programming command
Data cannot be written to a protected block. When automatic programming is finished, it automatically
The automatic chip erase operation starts when the sixth bus write cycle of the command cycle is
This condition can be checked by monitoring FCFLCS<RDY/BSY> . While no automatic verify
Also, any protected blocks cannot be erased. If all the blocks are protected, the automatic chip erase
For returning to the read mode, it is necessary to execute hardware reset to reset the device. In this
Note:Software reset becomes ineffective in bus write cycles on and after the fourth bus write
Automatic chip erase
cycle of the automatic page programming command.
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TMPM333FDFG/FYFG/FWFG