TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 262

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.11
Receive
10.11
10.11.1
10.11.2
10.11.3
10.11.2.1
10.11.2.2
10.11.3.1
SIOCLK clock pulses are used in receiving a single data bit and the data symbol is sampled at the seventh, eighth,
and ninth pulses. From these three samples, majority logic is applied to decide the received data.
Receive interrupt(INTRXx)
Receive
The receive counter is a 4-bit binary counter and is up-counted by SIOCLK. In the UART mode, sixteen
the shift clock outputted to the SCLK pin.
rising or falling edge of SCLK input signal depending on the SCxCR <SCLKS> setting.
normal start bit is detected.
the interrupt INTRXx is generated.
full flag (SCxMOD2<RBFLL>) is set to "1". The receive buffer full flag is "0" cleared by reading the receive
buffer.
Receive shift register
Receive Counter
Receive Control Unit
Receive Operation
SCxMOD2<RBFLL>
In the SCLK output mode with SCxCR <IOC> set to "0", the RXD pin is sampled on the rising edge of
In the SCLK input mode with SCxCR <IOC> set to "1", the serial receive data RXD pin is sampled on the
The receive control unit has a start bit detection circuit, which is used to initiate receive operation when a
The received data is stored by 1 bit in the receive shift register. When a complete set of bits has been stored,
When the double buffer is enabled, the data is moved to the receive buffer (SCxBUF) and the receive buffer
I/O interface mode
UART Mode
Receive Buffer
Receive buffer
Figure 10-4 Receive Buffer Operation
DATA 1
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DATA 1
TMPM333FDFG/FYFG/FWFG
Receive buffer read