TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 77

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

Note:
Table 7-1 Exception Types and Priority
<PRI_n> bit is defined as a 3-bit configuration with this product.
7~10
16~
No.
11
12
13
14
15
1
2
3
4
5
6
(2)
(3)
Reset
Non-Maskable Interrupt
Hard Fault
Memory Management
Bus Fault
Usage Fault
Reserved
SVCall
Debug Monitor
Reserved
PendSV
SysTick
External Interrupt
to that exception. Memory Management, Bus Fault and Usage Fault exceptions can be enabled or dis-
abled. If a disabled exception occurs, it is handled as Hard Fault.
Note 1: This product does not contain the MPU.
Note 2: External interrupts have different sources and numbers in each product. For details, see "7.5.1.5
If multiple exceptions occur simultaneously, the CPU takes the exception with the highest priority.
Table 7-1 shows the priority of exceptions. "Configurable" means that you can assign a priority level
Exception detection
Priority setting
Exception type
・ Priority levels
・ Priority grouping
are set to <PRI_n> bit in the system handler priority register.
priority varies from 3 bits to 8 bits depending on products. Thus, the range of priority values
you can specify is different depending on products.
The highest priority is "0". If multiple elements with the same priority exist, the smaller the
number, the higher the priority becomes.
interrupt and reset control register, <PRI_n> can be divided into the pre-emption priority and
the sub priority.
emption priority, then it is compared with the sub priority. If the sub priority is the same as the
priority, the smaller the exception number, the higher the priority.
List of Interrupt Sources".
The external interrupt priority is set to the interrupt priority register and other exceptions
The configuration <PRI_n> can be changed, and the number of bits required for setting the
In the case of 8-bit configuration, the priority can be configured in the range from 0 to 255.
The priority group can be split into groups. By setting the <PRIGROUP> of the application
A priority is compared with the pre-emption priority. If the priority is the same as the pre-
−3 (highest)
−2
−1
Configurable
Configurable
Configurable
−
Configurable
Configurable
−
Configurable
Configurable
Configurable
Priority
Reset pin, WDT or SYSRETREQ
NMI pin or WDT
Fault that cannot activate because a higher-priority fault is being handled
or it is disabled
Exception from the Memory Protection Unit (MPU) (Note 1)
Instruction fetch from the Execute Never (XN) region
Access violation to the Hard Fault region of the memory map
Undefined instruction execution or other faults related to instruction ex-
ecution
System service call with SVC instruction
Debug monitor when the CPU is not faulting
Pendable system service request
Notification from system timer
External interrupt pin or peripheral function (Note 2)
Page 57
Description
TMPM333FDFG/FYFG/FWFG