TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 436

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15.3
On-board Programming of Flash Memory (Rewrite/Erase)
Table 15-16 Address Bit Configuration for Bus Write Cycles
[TMPM333FDFG/FYFG/FWFG]
[TMPM333FDFG/FYFG]
[TMPM333FWFG]
Normal com-
mands
ID-READ
Block erase
Auto page
program-
ming
Protection bit
program-
ming
Protection bit
erase
Block erase
Auto page
program-
ming
Protection bit
program-
ming
Protection bit
erase
Address
15.3.1.7
Address setting can be performed according to the normal bus write cycle address configuration from the first
bus cycle. "0" is recommended" in the Table 15-16 Address Bit Configuration for Bus Write Cycles can be
changed as necessary.
Flash area
Flash area
Flash area
Flash area
Flash area
Flash area
[31:19]
Table 15-16 is used in conjunction with Table 15-15 "Flash Memory Access from the Internal CPU."
Addr
Address bit configuration for bus write cycles
Block selection (Table 15-17)
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
PBA: Protection bit address (Set the seventh bus write cycle address for protection bit programming
Addr
Protection bit selection
(Table 15-19)
(Table 15-18)
(Table 15-19)
[18]
Protection bit
Protection bit
Protection bit
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
"0" is recommended.
"0" is recommended.
selection
selection
selection
Block selection
(Table 15-17)
(Table 15-18)
BA: Block address (Set the sixth bus write cycle address for block erase operation)
BA: Block address (Set the sixth bus write cycle address for block erase operation)
Addr
[17]
IA: ID address (Set the fourth bus write cycle address for ID-Read operation)
Addr
[16]
Page selection
Normal bus write cycle address configuration
Addr
[15]
ID address
Page selection
"0" is recommended.
Page 416
Addr
[14]
Fixed to "0".
Fixed to "0".
Fixed to "0".
[13:11]
Addr
Addr[1:0]="0" (fixed) , Others:0 (recommended)
Command
Addr[1:0]="0" (fixed) , Others:0 (recommended)
Addr[1:0]="0" (fixed) , Others:0 (recommended)
Addr
(Table 15-18)
[10]
Protection bit
selection
TMPM333FDFG/FYFG/FWFG
Addr
(Table 15-18)
Protection bit
[9]
Others:0 (recommended)
selection
Addr[1:0]="0" (fixed)
Others:0 (recommended)
Addr
Addr[1:0]="0" (fixed)
[8]
Others:0 (recommended)
Others:0 (recommended)
Addr[1:0]="0" (fixed)
Addr[1:0]="0" (fixed)
Others:0 (recommen-
Addr[1:0]="0" (fixed)
Addr[1:0]="0" (fixed)
Addr[1:0]="0" (fixed)
(recommended)
(recommended)
Others:0
Others:0
Addr
[7:0]
ded)