TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 341

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.3.9
31-6
5
4-1
0
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit
−
ADOBIC1
ADREGS1[3:0]
ADOBSV1
Bit Symbol
ADMOD5 (Mode Control Register 5)
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R/W
R/W
Type
30
22
14
0
0
0
6
0
Read as 0.
Set the AD monitor function interrupt 1.
0: If the value of the conversion result is smaller than the comparison register 1, an interrupt is generated.
1: If the value of the conversion result is bigger than the comparison register 1, an interrupt is generated.
Select a target conversion result register when using the AD monitor function 1 (See the below table).
AD monitor function 1
0: Disable
1: Enable
-
-
-
-
ADOBIC1
29
21
13
0
0
0
5
0
-
-
-
<ADREGS1[3:0]>
Page 321
0000
0001
0010
0011
−
28
20
12
0
0
0
4
0
-
-
-
register to be com-
Conversion result
27
19
11
Function
0
0
0
3
0
-
-
-
ADREG2A
ADREG3B
ADREG08
ADREG19
pared
ADREGS1
−
26
18
10
0
0
0
2
0
-
-
-
TMPM333FDFG/FYFG/FWFG
<ADREGS1[3:0]>
0100
0101
0110
0111
1xxx
25
17
0
0
9
0
1
0
-
-
-
register to be com-
Conversion result
ADOBSV1
ADREG4C
ADREG5D
ADREGSP
ADREG6E
ADREG7F
pared
24
16
0
0
8
0
0
0
-
-
-