TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 308

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.6
Data Transfer Procedure in the I2C Bus ModeI2C
11.6.3
11.6.3.1
SBI is in the master or slave mode.
INTSBIx interrupt
if MST = 0
Then go to the slave-mode processing.
if TRX = 0
Then go to the receiver-mode processing.
if LRB = 0
Then go to processing for generating the stop condition.
SBIxCR1
SBIxDBR
End of interrupt processing.
At the end of a data word transfer, the INTSBIx interrupt is generated to test <MST> to determine whether the
Transferring a Data Word
(1)
Test <TRX> to determine whether the SBI is configured as a transmitter or a receiver.
Master mode (<MST> = "1")
eight bits, the data is written into SBIxDBR. If the data has different length, <BC[2:0]> and <ACK>
are programmed and the transmit data is written into SBIxDBR.Writing the data makes <PIN> to "1",
causing the SCL pin to generate a serial clock for transferring a next data word, and the SDA pin to
transfer the data word.
and the SCL pin is pulled to the "Low" level.
Test <LRB>. If <LRB> is "1", that means the receiver requires no further data.
The master then generates the stop condition as described later to stop transmission.
If <LRB> is "0", that means the receiver requires further data.If the next data to be transmitted has
After the transfer is completed, the INTSBIx interrupt request is generated, <PIN> is cleared to "0",
To transmit more data words, test <LRB> again and repeat the above procedure.
Note:X; Don’t care
Transmitter mode (<TRX> = "1")
←
←
X
X
X
X
X
X
X
X
0
X
X
X
X
X
Page 288
X
X
Specifies the number of bits to be transmitted and
specify whether ACK is required.
Writes the transmit data.
TMPM333FDFG/FYFG/FWFG