TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 326

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.8
Control in SIO mode
<SIOS>
<SIOF>
<SEF>
SCKx pin (output)
SOx pin
SIx pin
INTSBIx
interrupt request
SBIxDBR
11.8.2.3
SBIxCR1<SIOS> to "1" enables transmission and reception.The transmit data is output through the SOx pin
at the falling of the serial clock, and the received data is taken in through the SI pin at the rising of the serial
clock, with the least-significant bit (LSB) first. Once the shift register is loaded with the 8-bit data, it transfers
the received data to SBIxDBR and the INTSBIx interrupt request is generated.The interrupt service program
reads the received data from the data buffer register and writes the next transmit data. Because SBIxDBR is
shared between transmit and receive operations, the received data must be read before the next transmit data
is written.
is read and the next transmit data is written.
Therefore, the received data must be read and the next transmit data must be written before the next shift
operation is started.The maximum data transfer rate for the external clock operation varies depending on the
maximum latency between when the interrupt request is generated and when the transmit data is written.
output in a period from setting <SIOF> to "1" to the falling edge of SCK.
to "1" in the INTSBIx interrupt service program. If <SIOS> is cleared, transmission and reception continue
until the received data is fully transferred to SBIxDBR. The program checks SBIxSR<SIOF> to determine
whether transmission and reception have come to an end. <SIOF> is cleared to "0" at the end of transmission
and reception.If <SIOINH> is set to "1", the transmission and reception is aborted immediately and <SIOF>
is cleared to "0".
Set the control register to the transfer/receive mode. Then writing the transmit data to SBIxDBR and setting
In the internal clock operation, the serial clock will be automatically in the wait state until the received data
In the external clock mode, shift operations are executed in synchronization with the external serial clock.
At the beginning of transmission, the same value as in the last bit of the previously transmitted data is
Transmission and reception can be terminated by clearing <SIOS> to "0" or setting SBIxCR1<SIOINH>
Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongoing
Write the transmitted
data(a)
8-bit transmit/receive mode
Figure 11-20 Transmit/Receive Mode (Example: Internal Clock)
transmission and reception must be completed by clearing <SIOS> to "0" and the last received
data must be read before the transfer mode is changed.
*
a
a
c
0
0
a
c
1
1
a
c
2
2
a
c
3
3
a
c
4
4
a
c
5
5
Read the received
data(c)
Page 306
a
c
6
6
a
c
7
7
c
Write the transmitted
data(b)
b
b
d
0
0
b
d
1
1
b
d
2
2
<SIOS> is cleard.
b
d
3
3
TMPM333FDFG/FYFG/FWFG
b
d
4
4
b
d
5
5
b
d
6
6
Read the received
data(d)
b
d
7
7
d