TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 192

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8.4
Appendix (Port setting List)
8.4
8.4.1
Appendix (Port setting List)
The following table shows the register setting for each function.
Initialization of the ports where the [・] does not exist in the "After reset" field is set to "0" for all register settings.
Setting for the bit "x" can be arbitrarily-specified.
Port A Setting
Table 8-6 Port Setting List (Port A)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Pin
Type
Port
T12
T6
T9
T9
T9
T9
T9
T1
Input Port
Output Port
TMS(Input)/
SWDIO(I/O)
Input Port
Output Port
TCK(Input)/
SWCLK(Input)
Input Port
Output Port
TRACECLK(Output)
Input Port
Output Port
TRACEDATA0(Output)
Input Port
Output Port
TRACEDATA1(Output)
Input Port
Output Port
TRACEDATA2(Output)
Input Port
Output Port
TRACEDATA3(Output)
Input Port
Output Port
Function
Page 172
reset
After
・
・
PACR
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
PAFR1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
PAPUP
x
x
1
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
TMPM333FDFG/FYFG/FWFG
PAPDN
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
PAIE
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0