TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 398

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15.2
Operation Mode
15.2.3
15.2.3.1
TMPM333FDFG/FYFG/FWFG on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode
is selected upon reset, the boot ROM is mapped to the address region including the interrupt vector table while
the flash memory is mapped to an address region different from it.
TMPM333FDFG/FYFG/FWFG is connected to an external host controller. Via this serial link, a programming
routine is downloaded from the host controller to the TMPM333FDFG/FYFG/FWFG on-chip RAM. Then, the
flash memory is re-programmed by executing the programming routine. The host sends out both commands and
programming data to re-program the flash memory. Communications between the SIO0 and the host must follow
the protocol described later. To secure the contents of the flash memory, the validity of the application’s password
is verified before a programming routine is downloaded into the on-chip RAM. If password matching fails, the
transfer of a programming routine itself is aborted. As in the case of User Boot mode, all interrupts including the
non-maskable interrupt (NMI) must be disabled in Single Boot mode while the flash memory is being erased or
programmed. In Single Boot mode, the boot-ROM programs are executed in Normal mode.
Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption
during subsequent Single-Chip (Normal mode) operations.
In Single Boot mode, the flash memory can be re-programmed by using a program contained in the
Single Boot mode allows for serial programming of the flash memory. Channel 0 of the SIO (SIO0) of the
Single Boot Mode
(1)
(2-A) Using the Program in the On-Chip Boot ROM
the programming routine. Since a programming routine and programming data are transferred via the
SIO (SIO0), the SIO0 must be connected to a host controller. Prepare a programming routine (a) on the
host controller.
The flash block containing the older version of the program code need not be erased before executing
Step-1
TMPM333FDFG/FYFG/FWFG
Boot ROM
(or erased state)
Old application
program code
Flash memory
Page 378
(I/O)
SIO0
RAM
(Host)
(a) Programming routine
New application
program code
TMPM333FDFG/FYFG/FWFG