LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 12
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LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 12 of 769
- Download datasheet (18Mb)
Lattice Semiconductor
LatticeECP2/M Hardware Checklist
LatticeECP3 and LatticeECP2M High-Speed Backplane Measurements
Section III. LatticeECP2/M Family Handbook Revision History
SED Flow ......................................................................................................................................................... 17-5
SED Run Time ................................................................................................................................................. 17-6
Sample Code ................................................................................................................................................... 17-7
Technical Support Assistance.......................................................................................................................... 17-8
Revision History ............................................................................................................................................... 17-9
Introduction ...................................................................................................................................................... 18-1
Power Supplies ................................................................................................................................................ 18-1
Configuration.................................................................................................................................................... 18-2
I/O Interface and Critical Pins .......................................................................................................................... 18-4
Checklist........................................................................................................................................................... 18-5
Technical Support Assistance.......................................................................................................................... 18-6
Revision History ............................................................................................................................................... 18-6
Introduction ...................................................................................................................................................... 19-1
Eye Diagram Experiment ................................................................................................................................. 19-1
Data Rate Experiment...................................................................................................................................... 19-5
Conclusions and Design Guidelines ................................................................................................................ 19-6
References....................................................................................................................................................... 19-7
Technical Support Assistance.......................................................................................................................... 19-7
Revision History ............................................................................................................................................... 19-7
Revision History ............................................................................................................................................... 20-1
SEDINPROG........................................................................................................................................... 17-3
SEDDONE .............................................................................................................................................. 17-4
SEDERR ................................................................................................................................................. 17-4
VHDL Example........................................................................................................................................ 17-7
Verilog Example ...................................................................................................................................... 17-8
LatticeECP2M SERDES/PCS Power Supplies ....................................................................................... 18-1
Power Supply Sequencing ...................................................................................................................... 18-2
Power Supply Ramp ............................................................................................................................... 18-2
Power Estimation .................................................................................................................................... 18-2
JTAG Interface ........................................................................................................................................ 18-3
I/O Pin Assignments Around V
PLLCAP .................................................................................................................................................. 18-4
DDR/DDR2 Memory Interface Pin Assignments..................................................................................... 18-5
True-LVDS Output Pin Assignments....................................................................................................... 18-5
HSTL and SSTL Pin Assignments .......................................................................................................... 18-5
PCI Clamp Pin Assignments ................................................................................................................... 18-5
Backplane Specifications ........................................................................................................................ 19-2
Test Setup Parameters ........................................................................................................................... 19-2
Eye Diagram Measurements................................................................................................................... 19-2
Results and Conclusion .......................................................................................................................... 19-5
Backplane Specifications ........................................................................................................................ 19-5
Test Setup Parameters ........................................................................................................................... 19-5
Data Rate Measurements ....................................................................................................................... 19-6
Results and Conclusions......................................................................................................................... 19-6
CCPLL.................................................................................................................................. 18-4
11
LatticeECP2/M Family Handbook
Table of Contents
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