LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 629

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Table 12-5. IDDRMFX1A Ports
Figure 12-14 shows the LatticeECP2 Input Register Block configured to function in the IDDRXMFX1A mode.
The DDR registers are designed to use Edge clock routing on the I/O side and the primary clock on the FPGA side.
The ECLK input is used to connect to the DQS strobe coming from the DQS delay block (DQSBUFC primitive). The
CLK1 and CLK2 inputs should be connected to the slow system (FPGA) clock. DDRCLKPOL is an input from the
DQS Clock Polarity tree. This signal is generated by the DQS Transition detect circuit in the hardware. The addi-
tional clock transfer registers are shared with the output register block.
Figure 12-14. Input Register Block in IDDRMFX1A Mode
Figure 12-15 shows the IDDRMFX1A timing waveform.
ECLK
CLK1
DATA
D
ECLK
RST
CLK1
CLK2
CE
DDRCLKPOL
QA
QB
Note:
DDRCLKPOL
Port Name
The DDRCLKPOL input to IDDRMFX1A should be connected to the DDRCLKPOL output of DQSBUFC.
B
A
DDR Registers
I/O
O
O
I
I
I
I
I
I
I
DDR Data
The phase shifted DQS should be connected to this input
Reset
Slow FPGA CLK
Slow FPGA CLK
Clock enable
DDR clock polarity signal
Data at the positive edge of the CLK
Data at the negative edge of the CLK
C
IDDRMFX1A
12-11
Synchronization
Registers
Description
E
D
CLK2
High-Speed I/O Interface
Clock Transfer
Registers
H
I
LatticeECP2/M
QB
QA