LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 706
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 706 of 769
- Download datasheet (18Mb)
Lattice Semiconductor
Figure 15-2. Multiple FPGAs, One SPI Serial Flash
SPIm Mode
Externally, except for the CFG pins, SPIm mode looks like SPI mode, they use the same SPI Serial Flash devices,
and are wired to the FPGA in the same way (see Figure 15-6). The SPIm mode does not support multiple FPGAs
being configured from one SPI serial Flash as shown in Figure 15-2. Internally the two modes are treated differ-
ently.
SPI mode treats the SPI Serial Flash as a single block of storage starting at address zero. The SPIm mode treats
the SPI flash memory as discrete blocks of memory rather than a single block of memory. This allows the storage
of separate configuration images in separate blocks of memory. SPIm supports dual configuration (or boot) images,
here referred to as a “golden” image and a primary image.
A golden image is used when there is the possibility that corrupt data could be inadvertently loaded into the SPI
Serial Flash, such as during remote updates. For instance, if the Flash erase or program procedure is interrupted,
perhaps due to a power failure, then the Flash will contain corrupt data and the system could be rendered inopera-
ble. Ideally the FPGA should detect that the data is corrupt and boot from a known good, or golden, boot image.
This is exactly what SPIm does.
The golden image is stored at the beginning of the Flash address space; the updatable, or primary, image is above
the golden image. During configuration, if the FPGA detects data corruption in the primary image, it will automati-
cally reboot from the golden image. Each time the FPGA powers up, the PROGRAMN pin is toggled, or a JTAG
Refresh instruction is issued, it will try to configure from the primary image first. Note that if the LatticeECP2/M
detects that the data in the golden image is corrupt as well INITN will be driven low and the part will stop trying to
configure.
Dual Boot Image Setup
In order to use dual configuration files the files must first be properly stored within the SPI Serial Flash. Lattice
ispVM™ System software makes this easy.
Note: This method is not available when using encrypted bitstream files with the LatticeECP2/M S-Series devices.
Please refer to the LatticeECP2/M S-Series Configuration Encryption Usage Guide, TN1109, for more information
about using encrypted bitstream files.
DONE
SPIFASTN
PROGRAMN
SPI Serial
Flash
/CS
Q
C
D
CCLK
D7/SPID0
BUSY/SISPI
DI/CSSPI0N
D0/SPIFASTN
Lattice FPGA
SPI Mode
DOUT
CFG2
CFG1
CFG0
15-10
LatticeECP2/M sysCONFIG Usage Guide
CCLK
DI/CSSPI0N
Lattice FPGA
Slave Serial
DOUT
CFG2
CFG1
CFG0
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