LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 545

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Verilog:
VHDL:
Not supported. For back annotation simulation LOCK_DELAY needs to be set in the preference file. Below is an
example for the PLL.
DLL Library Symbols
Figure 10-19. DLL Library Symbols
DLL Library Definitions
The Lattice library contains library elements to allow designers to utilize the DLL. These library elements use the
DLL attributes defined in the “DLL Attributes” section.
The two modes of operation are presented as library elements as listed below.
Table 10-9. DLL Library Elements
DLL Library Element I/Os
Table 10-10. DLL Library Element I/O Descriptions
TRDLLA
CIDDLLA
CLKI
CLKFB
RSTN
ALUHOLD
UDDCNTL
DCNTL[8:0]
CLKOP
CLKOS
LOCK
Note: Refer to device data sheet for frequency specifications.
Library Element
Name
Signal
defparam mydll.mypll_0_0.LOCK_DELAY=500;
mydll dll_inst(.CLKI(clkin), .CLKOP(clk1), .CLKOS(clk2),
ASIC “pll/pll_0_0” TYPE “EHXPLLA” LOCK_DELAY=200;
Time Reference Delay DLL
Clock Injection Delay DLL
(Four Delay Cell Mode)
I/O
O
O
O
O
Mode of Operation
I
I
I
I
I
CLKI
RSTN
ALUHOLD
UDDCNTL
Clock input pin from dedicated clock input pin, other I/O or logic block.
Clock feedback input pin from dedicated feedback input pin, internal feedback, other I/O or
logic block. This signal is not user selectable.
Active low synchronous reset. From dedicated pin or internal node.
“1” freezes the ALU. For TRDLLA and CIDDLLA.
Active high synchronous enable signal from CIB for updating digital control to PIC delay. It
must be driven high at least two clock cycles.
Digital delay control code signals.
The primary clock output for all possible modes.
The secondary clock output with finer phase shift and/or division by 2 or by 4.
Active high phase lock indicator. Lock means the reference and feedback clocks are in phase.
TRDLLA
CLKOP
CLKOS
DCNTL
LOCK
This mode generates four phases of the clock, 0°, 90°, 180°, 270°, along
with the control setting used to generate these phases.
This mode removes the clock tree delay, aligning the external feedback
clock to the reference clock. It has a single output coming from the fourth
delay block.
10-21
CLKI
CLKFB
RSTN
ALUHOLD
Description
LatticeECP2/M sysCLOCK PLL/DLL
CIDDLLA
Description
CLKOP
CLKOS
LOCK
Design and Usage Guide