LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 2

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

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July 2011
Section I. LatticeECP2/M Family Data Sheet
Introduction
Architecture
Features ............................................................................................................................................................. 1-1
Introduction ........................................................................................................................................................ 1-2
Architecture Overview ........................................................................................................................................ 2-1
PFU Blocks ........................................................................................................................................................ 2-3
Routing............................................................................................................................................................... 2-6
sysCLOCK Phase Locked Loops (GPLL/SPLL) ................................................................................................ 2-6
Delay Locked Loops (DLL)................................................................................................................................. 2-8
GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only) .................................................. 2-10
Clock Dividers .................................................................................................................................................. 2-10
Clock Distribution Network ............................................................................................................................... 2-11
sysMEM Memory ............................................................................................................................................. 2-19
sysDSP™ Block ............................................................................................................................................... 2-21
Optimized DSP Functions ................................................................................................................................ 2-28
Slice .......................................................................................................................................................... 2-3
Modes of Operation................................................................................................................................... 2-5
General Purpose PLL (GPLL) ................................................................................................................... 2-6
Standard PLL (SPLL) ................................................................................................................................ 2-7
DLLDELA Delay Block .............................................................................................................................. 2-9
PLL/DLL Cascading .................................................................................................................................. 2-9
Primary Clock Sources............................................................................................................................ 2-11
Secondary Clock/Control Sources .......................................................................................................... 2-13
Edge Clock Sources................................................................................................................................ 2-14
Primary Clock Routing ............................................................................................................................ 2-15
Dynamic Clock Select (DCS) .................................................................................................................. 2-15
Secondary Clock/Control Routing ........................................................................................................... 2-15
Slice Clock Selection............................................................................................................................... 2-17
Edge Clock Routing ................................................................................................................................ 2-18
sysMEM Memory Block........................................................................................................................... 2-19
Bus Size Matching .................................................................................................................................. 2-19
RAM Initialization and ROM Operation ................................................................................................... 2-19
Memory Cascading ................................................................................................................................. 2-19
Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-19
Memory Core Reset ................................................................................................................................ 2-20
EBR Asynchronous Reset....................................................................................................................... 2-20
sysDSP Block Approach Compared to General DSP ............................................................................. 2-21
sysDSP Block Capabilities ...................................................................................................................... 2-21
MULT sysDSP Element .......................................................................................................................... 2-23
MAC sysDSP Element ............................................................................................................................ 2-24
MULTADDSUB sysDSP Element ........................................................................................................... 2-25
MULTADDSUBSUM sysDSP Element ................................................................................................... 2-26
Clock, Clock Enable and Reset Resources ............................................................................................ 2-26
Signed and Unsigned with Different Widths............................................................................................ 2-27
OVERFLOW Flag from MAC .................................................................................................................. 2-27
IPexpress™............................................................................................................................................. 2-28
Resources Available in the LatticeECP2/M Family ................................................................................. 2-28
LatticeECP2/M Family Handbook
1
Table of Contents