LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 534

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
PHASE/DUTY_CNTL
This attribute is designed to select the Phase Adjustment/Duty Cycle Select mode. If the attribute is set to
“DYNAMIC” the Phase Adjustment/Duty Cycle Select control switches between dynamic and static, depending
upon the input logic of the DPAMODE pin. If the attribute is set to “STATIC”, Dynamic Phase Adjustment/Duty Cycle
Select inputs are ignored in this mode.
CLKOS/CLKOK Select
Users select these output clocks only when they are used in the design.
CLKOP/CLKOS/CLKOK BYPASS
These bypasses are enabled if set. The CLKI is routed directly to the corresponding output clock.
RESET/RSTK Select
Users select these reset signals only when they are used in the design.
LatticeECP2/M PLL Modules
When the user creates a PLL module using IPexpress, the module will consist of a wrapper around the PLL library
element and any additional logic required for the module. Figure 10-10 shows a diagram of a typical PLL module.
The module port names can be different than the library element is some cases. The user will see the module port
names in the IPexpress window and also in the source code file for the generated module. These are the ports that
will be connected in the user's design. IPexpress also creates an instantiation template file that shows the user how
to instantiate the PLL module in their design. The user can import the *.LPC (or *.IPX for Diamond) file into their
project or the generated source code file.
Figure 10-10. LatticeECP2/M Typical PLL Module Generated by IPexpress
The PLL module shown in Figure 10-10 represents an example where the user has chosen to use the CLKOP and
CLKOS ports, with a PLL reset signal, PLL lock signal, and dynamic phase and dynamic duty cycle. It also uses
CLKOP feedback so the software will connect the CLKOP signal to the CLKFB port and use the primary clock tree
to route this signal. The user would connect their signals to the CLKI, RST, DPAMODE, DPHASE[3:0],
DDUTY[3:0], CLKOP, CLKOS, and LOCK signals.
LatticeECP2/M PLL Library Definitions
All LatticeECP2/M devices support two General Purpose PLLs (GPLLs) which are full-featured PLLs. In addition,
some of the larger devices have two to six Standard PLLs (SPLLs) that have a subset of the GPLL functionalities.
Two PLL library elements are defined for LatticeECP2/M PLL implementation. Figure 10-11 shows the
LatticeECP2/M PLL library symbols. The GPLL may be configured as either EPLLD or EHXPLLD. The SPLL can
be configured as EPLLD only.
DPHASE[3:0]
DDUTY[3:0]
DPAMODE
CLKI
RST
Additional
Logic
10-10
RST
RSTK
CLKI
CLKFB
DPAMODE
DRPAI[3:0]
DFPAI[3:0]
LatticeECP2/M sysCLOCK PLL/DLL
EPLLD
CLKINTFB
CLKOP
CLKOS
CLKOK
LOCK
Design and Usage Guide
CLKOP
CLKOS
LOCK