LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 30
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LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 30 of 769
- Download datasheet (18Mb)
Architecture
Lattice Semiconductor
LatticeECP2/M Family Data Sheet
Primary Clock Routing
The clock routing structure in LatticeECP2/M devices consists of a network of eight primary clock lines (CLK0
through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center
of the device. All the clock sources are connected to these muxes. Figure 2-13 shows the clock routing for one
quadrant. Each quadrant mux is identical. If desired, any clock can be routed globally
Figure 2-13. Per Quadrant Primary Clock Selection
Primary Clock Sources: PLLs + DLLs + CLKDIVs + PIOs + Routing
35:1
35:1
35:1
35:1
35:1
35:1
32:1
32:1
32:1
32:1
DCS
DCS
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
8 Primary Clocks (CLK0 to CLK7) per Quadrant
Dynamic Clock Select (DCS)
The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent
input clock sources without any glitches or runt pulses. This is achieved regardless of when the select signal is tog-
gled. There are two DCS blocks per quadrant; in total, there are eight DCS blocks per device. The inputs to the
DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7
(see Figure 2-13).
Figure 2-14 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed
to other modes. For more information about the DCS, please see the list of additional technical documentation at
the end of this data sheet.
Figure 2-14. DCS Waveforms
CLK0
CLK1
SEL
DCSOUT
Secondary Clock/Control Routing
Secondary clocks in the LatticeECP2 devices are region-based resources. The benefit of region-based resources
is the relatively low injection delay and skew within the region, as compared to primary clocks. EBR/DSP rows and
a special vertical routing channel bound the secondary clock regions. This special vertical routing channel aligns
with either the left edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-15 shows
2-15
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