LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 550
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 550 of 769
- Download datasheet (18Mb)
Lattice Semiconductor
Figure 10-23. CLKDIV Application Examples
Release Behavior
The port “Release” is used to synchronize all outputs after RST is de-asserted. Figure 10-24 illustrates the Release
behavior.
Figure 10-24. CLKDIV Release Behavior
RELEASE
CDIV1
CDIV2
CDIV4
CDIV8
De-asserted RST
CLKI
RST
registered
Data
Data
CLK
8
8
Clock start counting
ECLK
RST
DLL
D
Q
CLKOP
CLKOS
CLKDIV
D
10-26
Q
Release synchronizes
GEARING
GEARING
(2x)
(2x)
outputs
LatticeECP2/M sysCLOCK PLL/DLL
Primary
Clock
(System Clock)
16
SCLK
16
Design and Usage Guide
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