LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 7

Software sysIO Attributes................................................................................................................................... 9-7

Design Considerations and Usage................................................................................................................... 9-10

Differential I/O Implementation......................................................................................................................... 9-11

Technical Support Assistance.......................................................................................................................... 9-12

Revision History ............................................................................................................................................... 9-12

Appendix A. HDL Attributes for Synplicity

Appendix B. sysIO Attributes Using the ispLEVER Design Planner User Interface......................................... 9-17

Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 9-18

Appendix D. Assigning sysIO Attributes Using Lattice Diamond Spreadsheet View ....................................... 9-21

Introduction ...................................................................................................................................................... 10-1

Clock/Control Distribution Network .................................................................................................................. 10-1

LatticeECP2/M Top Level View........................................................................................................................ 10-2

sysCLOCK PLL ................................................................................................................................................ 10-6

Functional Description...................................................................................................................................... 10-6

Open-Drain Control ................................................................................................................................... 9-6

Differential SSTL and HSTL Support ........................................................................................................ 9-6

PCI Support with Programmable PCICLAMP ........................................................................................... 9-7

Programmable Input Delay ....................................................................................................................... 9-7

IO_TYPE ................................................................................................................................................... 9-7

OPENDRAIN............................................................................................................................................. 9-8

DRIVE ....................................................................................................................................................... 9-8

PULLMODE .............................................................................................................................................. 9-9

PCICLAMP................................................................................................................................................ 9-9

SLEWRATE .............................................................................................................................................. 9-9

FIXEDDELAY.......................................................................................................................................... 9-10

INBUF ..................................................................................................................................................... 9-10

DIN/DOUT............................................................................................................................................... 9-10

LOC......................................................................................................................................................... 9-10

Banking Rules ......................................................................................................................................... 9-10

Differential I/O Rules ............................................................................................................................... 9-10

Assigning V

LVDS....................................................................................................................................................... 9-11

BLVDS .................................................................................................................................................... 9-11

RSDS ...................................................................................................................................................... 9-11

LVPECL .................................................................................................................................................. 9-12

Differential SSTL and HSTL.................................................................................................................... 9-12

VHDL Synplicity/Precision RTL Synthesis .............................................................................................. 9-13

Verilog Synplicity..................................................................................................................................... 9-15

Verilog Precision ..................................................................................................................................... 9-16

IOBUF ..................................................................................................................................................... 9-18

LOCATE.................................................................................................................................................. 9-18

USE DIN CELL........................................................................................................................................ 9-19

USE DOUT CELL.................................................................................................................................... 9-19

PGROUP VREF ...................................................................................................................................... 9-19

Primary Clocks ........................................................................................................................................ 10-3

Secondary Clocks ................................................................................................................................... 10-3

Edge Clocks ............................................................................................................................................ 10-3

Note on Primary Clocks .......................................................................................................................... 10-4

Specifying Clocks in the Design Tools .................................................................................................... 10-5

Primary-Pure and Primary-DCS.............................................................................................................. 10-5

Global Primary Clock and Quadrant Primary Clock ................................................................................ 10-5

Note on Edge Clocks .............................................................................................................................. 10-5

PLL Divider and Delay Blocks................................................................................................................. 10-6

REF1

/ V

REF2

Groups for Referenced Inputs.......................................................................... 9-11

and Precision

RTL Synthesis...................................................... 9-13

LatticeECP2/M Family Handbook

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