LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 549

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
CLKDIV Usage with Verilog - Example
module clkdiv_top(RST,CLKI,RELEASE,CDIV1,CDIV2,CDIV4,CDIV8);
input CLKI,RST,RELEASE;
output CDIV1,CDIV2,CDIV4,CDIV8;
CLKDIVB CLKDIBinst0 (.RST(RST),.CLKI(CLKI),.RELEASE(RELEASE),
defparam CLKDIBint0.GSR = "DISABLED";
endmodule
CLKDIV Example Circuits
The clock divider (CLKDIV) can divide a clock by 2 or 4 and drives a primary clock network. The clock dividers are
useful for providing the low-speed FPGA clocks for I/O shift registers (x2, x4) and DDR (x2, x4) I/O logic interfaces.
Divide by 8 is provided for slow speed/low power operation.
To guarantee a synchronous transfer in the I/O logic, the CLKDIV input clock must come from an edge clock and
the output drives a primary clock. In this case, they are phase matched. This is especially useful for synchronously
resetting the I/O logic when Mux/DeMux gearing is used in order to synchronize the entire data bus as shown in
Figure 10-23. Using the low skew characteristics of the edge clock routing, a reset can be provided to all bits of the
data bus to synchronize the Mux/DeMux gearing.
The second circuit shows that a DLL can replace CLKDIV for x2 and x4 applications.
CDIV1
CDIV2
CDIV4
CDIV8
);
end
.CDIV1(CDIV1),.CDIV2(CDIV2),.CDIV4(CDIV4),.CDIV8(CDIV8));
=> CDIV1sig,
=> CDIV2sig,
=> CDIV4sig,
=> CDIV8sig
10-25
LatticeECP2/M sysCLOCK PLL/DLL
Design and Usage Guide