LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 508

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Programmable Drive
Each LVCMOS or LVTTL, as well as some of the referenced (SSTL and HSTL) output buffers, has a programmable
drive strength option. This option can be set for each I/O independently. The drive strength settings available are
2mA, 4mA, 6mA, 8mA, 12mA, 16mA and 20mA. Actual options available vary by the I/O voltage. The user must
consider the maximum allowable current per bank and the package thermal limit current when selecting the drive
strength. Table 9-6 shows the available drive settings for each out the output standards.
Table 9-6. Programmable Drive Values for Single-ended Buffers
Programmable Slew Rate
Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured
for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows
designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling
edges.
Open-Drain Control
All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs. The user can imple-
ment an open drain output by turning on the OPENDRAIN attribute in the software.
Differential SSTL and HSTL Support
The single-ended driver associated with the complementary ‘C’ pad can optionally be driven by the complement of
the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers
to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driv-
ing complementary SSTL and HSTL signals (as required by the differential SSTL and HSTL clock inputs on syn-
chronous DRAM and synchronous SRAM devices respectively). This capability is also used in conjunction with off-
chip resistors to emulate LVPECL, and BLVDS output drivers.
PCI Support with Programmable PCICLAMP
Each sysIO buffer can be configured to support PCI33. The buffers on the bottom of the device (for LatticeECP2) or
on the left and bottom sides of the device (for LatticeECP2M) have an optional PCI clamp diode that may optionally
be specified in the ispLEVER design tools.
Programmable PCICLAMP can be turned ON or OFF. This option is available on each I/O independently on the
bottom side banks (for LatticeECP2) or on the left and bottom side banks (for LatticeECP2M).
HSTL15_I/ HSTL15D_I
HSTL18_I/ HSTL18D_I
SSTL25_I/ SSTL25D_I
SSTL25_II/ SSTL25D_II
SSTL18_II/SSTL18D_II
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
Single Ended I/O Standards
9-7
Programmable Drive (mA)
4, 8, 12, 16, 20
4, 8, 12, 16, 20
4, 8, 12, 16, 20
4, 8, 12, 16
16, 20
8, 12
8, 12
8, 12
4, 8
2, 6
4, 8
LatticeECP2/M sysIO
Usage Guide