LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 9

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
LatticeECP2/M Memory Usage Guide
LatticeECP2/M High-Speed I/O Interface
Introduction ...................................................................................................................................................... 11-1
Memories in LatticeECP2/M Devices............................................................................................................... 11-1
Utilizing IPexpress............................................................................................................................................ 11-2
Memory Modules.............................................................................................................................................. 11-6
Initializing Memory ......................................................................................................................................... 11-41
Technical Support Assistance........................................................................................................................ 11-42
Revision History ............................................................................................................................................. 11-43
Appendix A. Attribute Definitions.................................................................................................................... 11-44
Introduction ...................................................................................................................................................... 12-1
DDR and DDR2 SDRAM Interfaces Overview................................................................................................. 12-1
Implementing DDR Memory Interfaces with LatticeECP2/M Devices.............................................................. 12-3
Memory Read Implementation ....................................................................................................................... 12-14
Generic High Speed DDR Implementation .................................................................................................... 12-22
DDR Usage in ispLEVER IPexpress.............................................................................................................. 12-34
FCRAM (“Fast Cycle Random Access Memory”) Interface ........................................................................... 12-39
Board Design Guidelines ............................................................................................................................... 12-39
References..................................................................................................................................................... 12-39
Creating a New Simulation Project Using Simulation Wizard ............................................................... 10-48
IPexpress Flow........................................................................................................................................ 11-2
Single Port RAM (RAM_DQ) – EBR Based ............................................................................................ 11-6
True Dual Port RAM (RAM_DP_TRUE) – EBR Based ......................................................................... 11-11
Pseudo Dual Port RAM (RAM_DP) – EBR Based ................................................................................ 11-17
Read Only Memory (ROM) - EBR Based.............................................................................................. 11-20
First In First Out (FIFO, FIFO_DC) – EBR Based................................................................................. 11-23
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based........................................................ 11-35
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based .......................................................... 11-36
Distributed ROM (Distributed_ROM) – PFU Based .............................................................................. 11-39
Initialization File Format ........................................................................................................................ 11-41
Binary File ............................................................................................................................................. 11-41
Hex File ................................................................................................................................................. 11-42
Addressed Hex...................................................................................................................................... 11-42
DATA_WIDTH....................................................................................................................................... 11-44
REGMODE............................................................................................................................................ 11-44
RESETMODE ....................................................................................................................................... 11-44
CSDECODE.......................................................................................................................................... 11-44
WRITEMODE........................................................................................................................................ 11-44
GSR ...................................................................................................................................................... 11-44
DQS Grouping......................................................................................................................................... 12-3
DDR Software Primitives......................................................................................................................... 12-5
DLL Compensated DQS Delay Elements ............................................................................................. 12-14
DQS Transition Detect or Automatic Clock Polarity Select ................................................................... 12-14
Data Valid Module................................................................................................................................. 12-15
DDR I/O Register Implementation......................................................................................................... 12-15
Memory Read Implementation in Software ........................................................................................... 12-15
Read Timing Waveforms....................................................................................................................... 12-16
Memory Write Implementation .............................................................................................................. 12-19
Generic DDR Software Primitives ......................................................................................................... 12-23
Design Rules/Guidelines....................................................................................................................... 12-34
DDR Generic......................................................................................................................................... 12-35
Configuration Tab.................................................................................................................................. 12-36
DDR_MEM ............................................................................................................................................ 12-36
Configuration Tab.................................................................................................................................. 12-37
8
LatticeECP2/M Family Handbook
Table of Contents