LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 643

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LFE2-20E-5FN256I

Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r

Specifications of LFE2-20E-5FN256I

Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFE2-20E-5FN256I
Quantity:
1 831
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 12-29 shows the primitive symbol for the IDDRFXA mode.
Figure 12-29. IDDRFXA Symbol
Table 12-8 lists the port names and descriptions for the IDDRFXA primitive.
Table 12-8. IDDRFXA Port Names
Figure 12-31 shows the LatticeECP2 Input Register Block configured in the IDDRXFXA mode. CLK1 used to regis-
ter the DDR registers and the first set of synchronization registers. CLK2 is used by the third stage of registers and
should be clocked by the FPGA clock. These clock transfer registers are shared with the output register block.
Figure 12-30. Input Register Block configured as IDDRFXA
DATA
D
CLK1
CLK2
CE
RST
QA
QB
Port Name
I/O
O
O
I
I
I
I
I
DDR Registers
B
A
DDR data
This clock can be connected to the ECLK or the FPGA clock
This clock should be connected to the FPGA clock
Clock Enable signal
Reset to the DDR register
Data at the positive edge of the clock
Data at the negative edge of the clock
D
CLK1
CLK2
CE
RST
C
Edge Clock
IDDRFXA
12-25
IDDRFXA
CLK1
Synchronization
QA
QB
Registers
Description
E
D
FPGA Clock
CLK2
Clock Transfer
High-Speed I/O Interface
Registers
H
I
LatticeECP2/M
QB
QA

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