LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 406

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

June 2010
Introduction to PCS
The LatticeECP2M™ FPGA family combines a high-performance FPGA fabric, high-performance I/Os and large
embedded RAM in a single industry-leading architecture. All LatticeECP2M devices also feature up to 16 channels
of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. The PCS logic can be configured to
support numerous industry-standard, high-speed data transfer protocols.
Each channel of PCS logic contains dedicated transmit and receive SERDES for high-speed full-duplex serial data
transfers at data rates up to 3.125 Gbps. The PCS logic in each channel can be configured to support an array of
popular data protocols including Ethernet (1GbE and SGMII), PCI Express, CPRI, and OBSAI. In addition, the pro-
tocol-based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in design-
ing their own high-speed data interface.
The PCS also provides bypass modes that allow for a direct 8-bit or 10-bit interface from the SERDES to the FPGA
logic. Each SERDES pin can be independently DC-coupled and can allow for both high-speed and low-speed oper-
ation on the same SERDES pin for such applications as Serial Digital Video.
Features
• Up to 16 Channels of High-Speed SERDES
• Multiple Clock Rate Support
• Full Function Embedded Physical Coding Sub-layer (PCS) Logic Supporting Industry Standard Protocols
• Gigabit Ethernet Support
• PCI Express Support
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– 250 Mbps to 3.125 Gbps per channel
– 3.125Gbps operation with low 100mW power per channel
– Receive equalization and transmit pre-emphasis for small form factor backplane operation
– Supports PCI Express, Ethernet (1GbE and SGMII) plus multiple other standards
– Supports user specified generic 8b10b mode
– Beacon support for PCI Express
– Out-of-band signal interface for low speed inputs (video application)
– Separate reference clocks for each PCS quad allow easy handling of multiple protocol rates on a single
– Up to 16 channels of full-duplex data supported per device
– Multiple protocol support on one chip
– Supports popular 8b10b based packet protocols
– SERDES Only mode allows direct 8- or 10-bit interface to FPGA logic
– IEEE 1000BASE-X compliant
– 8b10b encoding/decoding
– Insertion of /I2/ symbols into the receive data stream for auto-negotiation support
– Comma character word alignment
– Clock Tolerance Compensation circuit
– x1 to x4 support in one PCS quad
– Integrated Word aligner
– 8b10b encoding/decoding
– Clock Tolerance Compensation circuit
– Electrical Idle and Receiver Detection support
– Support for Beacon Transmission and Beacon Detection
device
8-1
LatticeECP2M SERDES/PCS
Usage Guide
Technical Note TN1124
tn1124_03.4