LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 729
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 729 of 769
- Download datasheet (18Mb)
June 2010
Introduction
All Lattice FPGAs provide configuration data read security, meaning that a fuse can be set so that when the device
is read all zeros will be output instead of the actual configuration data. This kind of protection is common in the
industry and provides very good security if the configuration data storage is on-chip, such as with the LatticeXP™
and MachXO™ device families. However, if the configuration bitstream comes from an external boot device it is
quite easy to read the configuration data, allowing access to the FPGA design.
For this reason the “S” versions of LatticeECP2™ and LatticeECP2M™ offer the 128-bit Advanced Encryption
Standard (AES) to protect the bitstream. The user selects and has total control over the 128-bit key and no special
voltages are required to maintain the key within the FPGA.
This document explains the capabilities of this new security feature and how to take advantage of it.
General Configuration Process
Figure 16-1 is a block diagram describing the LatticeECP2/M “S” version bitstream encryption data paths. Refer to
this figure as you read the following sections.
Figure 16-1. LatticeECP2/M “S” Version Bitstream Encryption Block Diagram
Lattice FPGAs are configured by using the sysCONFIG™ interface or the JTAG interface (see Table 16-1).
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
SCM, SPI
CFG[2:0]
PCM
Bitstream_Burst
Disable Readback
MUX
JTAG
CONFIG_SECURE
JTAG Port
JTAG Direct Access (1532)
Decoder
PCM Readback
LatticeECP2/M S-Series Configuration
DATA
RawDecrypted
Decrypt
16-1
CRC Check
Encryption Key
Key Fuses
Programmer
Encryption Usage Guide
Decompressed
Decompress
Technical Note TN1109
SRAM Fuses
00100101100100
10100101000101
101100101……
Logic
User
tn1109_01.4
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