LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 540

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Table 10-7. User Parameters in the Configuration GUI
Frequency Mode
Divider Mode
CLKI
CLKFB
CLKOP
CLKOS
CLKOK
PLL Phase & Duty Option
Delay Adjust
Provide PLL Reset
Provide CLKOK Divider Reset
Import LPC to ispLEVER project
1. These values apply to SPLL. All other values apply to both GPLL and SPLL.
2. Phase Detector Input Frequency range 2 MHz to 50MHz.
3. For f
4. IPexpress gives the user the ability to select the GPLL, SPLL, or to let the software choose, based upon the settings in the Delay Adjust
section.
IN
User Parameters
< 5MHz, f
Frequency
Divider
Feedback Mode
Divider
Bypass
Desired Frequency
Divider
Tolerance
Actual Frequency
Enable
Bypass
Phase - Static
Duty - Static
Dynamic Phase
with 50% Duty
Dynamic Phase
with Dynamic Duty
Enable
Bypass
Desired Frequency
Divider
Tolerance
Actual Frequency
OUT_max
= 10 * f
IN
.
Desired input/output frequency
Desired input frequency and divider
settings
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Feedback Mode
Without external capacitor
With external capacitor
Bypass PLL: CLKOP = CLKI
Without external capacitor
With external capacitor
CLKOP Divider Setting (Divider Mode)
CLKOP tolerance users can tolerate
Actual frequency achievable, Read only
Enable CLKOS output clock
Bypass PLL: CLKOS = CLKI
CLKOS Static Phase Shift
CLKOS Static Duty Cycle Select
Dynamic Phase and 50% Duty Cycle
Dynamic Phase and Dynamic Duty Cycle
Enable CLKOK output clock
Bypass PLL: CLKOK = CLKI
Without external capacitor
With external capacitor
CLKOK Divider Setting (Divider Mode)
CLKOK tolerance users can tolerate
Actual frequency achievable, Read only
Dynamic/Static Mode selection
Dynamic/Static/No delay selection
Provide PLL Reset Port
Provide CLKOK Reset Port
Import .lpc file to ispLEVER project
Description
10-16
LatticeECP2/M sysCLOCK PLL/DLL
2,4,8,16,32,48, 64,80,96,112,128
0.0, 0.1, 0.2, 0.5, 1.0, 2.0, 5.0,
0.0, 0.1, 0.2, 0.5, 1.0, 2.0, 5.0,
Internal, CLKOP, User clock
Dynamic Mode/Static Mode
2 to 128 (all even numbers)
25 (33
25(331) MHz to 420 MHz
0°, 22.5°, 45°, .... , 337.5°
Dynamic/Static/No Delay
0.195 MHz to 210 MHz
0.016 MHz to 25 MHz
2 MHz to 420 MHz
5 MHz to 50 MHz
1
1 to 16 (12
1 to 16(12
) MHz to 420 MHz
Design and Usage Guide
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
Range
1 to 64
1 to 10
2 to 14
10.0
10.0
—
—
1
1
)
)
3
2
3
Static Mode
No Delay
100 MHz
100 MHz
50 MHz
Default
CLKOP
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
0.0
0.0
—
—
—
—
—
—
—
2
1
1
8
8
-
4