LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 756

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
I/O Interface and Critical Pins
There are nine I/O banks on every LatticeECP2/M device. V
configuration requirements should have the highest priority to determine the supply voltage levels.
I/O Pin Assignments Around V
The V
ment will keep “noisy” I/O pins away from “sensitive” pins, as shown in the BGA ball locations identified in
Figure 18-1. In this case, the sensitive pin is one of the V
highest switching frequency, the highest V
Figure 18-1, one can identify the “keep out” ball locations for potentially noisy signals.
Figure 18-1. “Quiet” Pin Assignment Considerations for BGA Packages
PLLCAP
An optional external capacitor can be used with both EXHPLLD and EPLLD to change the frequency response of
the on-chip loop filter. When an external capacitor is used, it allows the PLLs to extend the low-end of their operat-
ing ranges. IPexpress™ checks the phase detector frequency to determine if an external capacitor is required. The
allowable ranges for the PLL parameters with and without the external capacitor are described in the
LatticeECP2/M Family Data
Recommended optional external capacitor specifications:
• Value: 5.6 nF, +/- 20%
• Type: Ceramic chip capacitor, NPO dielectric
• Package: 1206 or smaller
Each device has two external capacitor pins, one for the left-side PLLs and one for the right-side PLLs. These pins
are in fixed locations. They are dedicated function pins that are NOT shared with user I/Os. When an external
capacitor pin is used by a PLL on one side of the device, it cannot be used by any other PLLs on the same side of
the device. This means that a maximum of two PLLs per device, one on the left side and one on the right side, can
have external capacitors attached.
Placing the capacitors at the PLLCAP pins only affects the PLL response when the software enables this feature.
This allows a designer to provide the capacitors (or unpopulated PCB pads) to the PLLCAP pins to utilize the lower
PLL frequencies if it becomes necessary for future changes to the design.
CCPLL
provides a “quiet” supply for the internal PLLs. For the best PLL jitter performance, careful pin assign-
Sheet.
5x5
5x5
5x5
5x5
5x5
CCPLL
CCIO
5x5
3x3
3x3
3x3
5x5
standard and the fastest output slew rates. For example, using
Sensitive
18-4
5x5
3x3
3x3
5x5
Pin
CCPLL
CCIO8
supply pins. The noisy”I/O pins generally have the
5x5
3x3
3x3
3x3
5x5
is the configuration I/O bank and as such, the
LatticeECP2/M Hardware Checklist
5x5
5x5
5x5
5x5
5x5