LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 5

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Supplemental Information
LatticeECP2/M Family Data Sheet Revision History
Section II. LatticeECP2/M Family Technical Notes
LatticeECP2M SERDES/PCS Usage Guide
LatticeECP2M Part Number Description.......................................................................................................... 5-14
Ordering Information ........................................................................................................................................ 5-14
For Further Information ...................................................................................................................................... 6-1
Revision History ................................................................................................................................................. 7-1
Introduction to PCS ............................................................................................................................................ 8-1
Features ............................................................................................................................................................. 8-1
Supported Standards ......................................................................................................................................... 8-2
Architecture Overview ........................................................................................................................................ 8-2
SERDES/PCS .................................................................................................................................................... 8-7
SERDES/PCS Functional Description ............................................................................................................. 8-12
Configuration GUIs........................................................................................................................................... 8-27
LatticeECP2M PCS in Gigabit Ethernet Mode ................................................................................................. 8-39
LatticeECP2M PCS in PCI Express Mode ....................................................................................................... 8-39
PCS Loopback Modes ..................................................................................................................................... 8-41
FPGA Interface Clocks Usage ......................................................................................................................... 8-42
SERDES/PCS Block Latency........................................................................................................................... 8-49
SERDES Client Interface (SCI)........................................................................................................................ 8-50
Other Design Considerations ........................................................................................................................... 8-56
LatticeECP2 S-Series Devices, Conventional Packaging......................................................................... 5-8
LatticeECP2 S-Series Devices, Lead-Free Packaging ........................................................................... 5-11
LatticeECP2M Standard Series Devices, Conventional Packaging........................................................ 5-15
LatticeECP2M Standard Series Devices, Lead-Free Packaging ............................................................ 5-18
LatticeECP2M S-Series Devices, Lead-Free Packaging ........................................................................ 5-23
PCS Quad ................................................................................................................................................. 8-2
PCS Quad and Channels.......................................................................................................................... 8-3
Per Channel PCS/FPGA Interface Ports................................................................................................... 8-4
Locating a PCS Quad ............................................................................................................................... 8-4
Detailed Channel Block Diagram .............................................................................................................. 8-4
SCI (SERDES Client Interface) Bus.......................................................................................................... 8-7
Using This Technical Note ........................................................................................................................ 8-7
I/O Definitions............................................................................................................................................ 8-9
SERDES ................................................................................................................................................. 8-12
Reference Clock Usage .......................................................................................................................... 8-13
Transmit Data.......................................................................................................................................... 8-16
Receive Data........................................................................................................................................... 8-16
Configuration File Description ................................................................................................................. 8-38
Gigabit Ethernet (1000BASE-X) Idle Insert............................................................................................. 8-39
Gigabit Ethernet Idle Insert and ff_correct_disp_ch[3:0] Signal Usage................................................... 8-39
Serial Loopback Mode ............................................................................................................................ 8-41
SERDES Parallel Loopback Mode.......................................................................................................... 8-41
PCS Parallel Loopback Mode ................................................................................................................. 8-41
2-to-1 Gearing ......................................................................................................................................... 8-44
Interrupts and Status............................................................................................................................... 8-52
SERDES Client Interface Application Example....................................................................................... 8-53
Dynamic Configuration of SERDES/PCS Quad...................................................................................... 8-54
SERDES Debug Capabilities .................................................................................................................. 8-54
Control Boxes and Buttons, Status Boxes and the Text Window ........................................................... 8-56
LatticeECP2M-35 vs. All Other LatticeECP2M Devices.......................................................................... 8-56
Engineering Samples vs. Production Devices ........................................................................................ 8-56
4
LatticeECP2/M Family Handbook
Table of Contents