LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 8
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LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
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Lattice Semiconductor
PLL Usage in IPexpress................................................................................................................................. 10-14
Frequency Calculation ................................................................................................................................... 10-17
PLL Modes of Operation ................................................................................................................................ 10-17
sysCLOCK DLL.............................................................................................................................................. 10-18
Clock Dividers (CLKDIV)................................................................................................................................ 10-23
DQSDLL and DQSDEL .................................................................................................................................. 10-29
DCS (Dynamic Clock Select) ......................................................................................................................... 10-29
Oscillator (OSCD) .......................................................................................................................................... 10-34
OSC Library Symbol (OSCD)......................................................................................................................... 10-34
Input Clock Sharing........................................................................................................................................ 10-36
Setting Clock Preferences.............................................................................................................................. 10-37
Power Supplies .............................................................................................................................................. 10-37
Technical Support Assistance........................................................................................................................ 10-38
Revision History ............................................................................................................................................. 10-38
Appendix A. Primary Clock Sources and Distribution .................................................................................... 10-39
Appendix B. PLL, DLL, CLKIDV and ECLK Locations and Connectivity ....................................................... 10-42
Appendix C. Clock Preferences ..................................................................................................................... 10-43
Appendix D. Lattice Diamond Usage Overview ............................................................................................. 10-46
PLL Inputs and Outputs .......................................................................................................................... 10-7
PLL Attributes.......................................................................................................................................... 10-9
LatticeECP2/M PLL Modules ................................................................................................................ 10-10
LatticeECP2/M PLL Library Definitions ................................................................................................. 10-10
Dynamic Delay Adjustment (EHXPLLD Only)....................................................................................... 10-11
Dynamic Phase/Duty Mode................................................................................................................... 10-11
Dynamic Phase Adjustment/Duty Cycle Select..................................................................................... 10-12
Optional External Capacitor .................................................................................................................. 10-13
Configuration Tab.................................................................................................................................. 10-14
Modes ................................................................................................................................................... 10-15
PLL Clock Injection Removal ................................................................................................................ 10-17
PLL Clock Phase Adjustment................................................................................................................ 10-18
DLL Overview........................................................................................................................................ 10-19
DLL Inputs and Outputs ........................................................................................................................ 10-19
DLL Attributes ....................................................................................................................................... 10-20
DLL Library Definitions.......................................................................................................................... 10-21
DLL Library Element I/Os...................................................................................................................... 10-21
DLL Modes of Operation ....................................................................................................................... 10-22
DLL Usage in IPexpress ....................................................................................................................... 10-23
CLKDIV Library Element Definition ....................................................................................................... 10-23
CLKDIV Declaration in VHDL Source Code.......................................................................................... 10-24
CLKDIV Usage with Verilog - Example ................................................................................................. 10-25
CLKDIV Example Circuits ..................................................................................................................... 10-25
Release Behavior.................................................................................................................................. 10-26
DLLDEL (Slave Delay Line) .................................................................................................................. 10-27
DCS Library Element Definition ............................................................................................................ 10-30
DCS Timing Diagrams .......................................................................................................................... 10-30
DCS Usage with VHDL - Example ........................................................................................................ 10-33
DCS Usage with Verilog - Example ...................................................................................................... 10-34
OSC Usage with VHDL - Example........................................................................................................ 10-35
OSC Usage with Verilog - Example ...................................................................................................... 10-35
Converting an ispLEVER Project to Lattice Diamond ........................................................................... 10-46
Importing an ispLEVER Design Project ................................................................................................ 10-46
Adjusting PCS Modules ........................................................................................................................ 10-46
Regenerate PCS Modules .................................................................................................................... 10-46
Using IPexpress with Lattice Diamond.................................................................................................. 10-47
7
LatticeECP2/M Family Handbook
Table of Contents
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