LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 99
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 99 of 769
- Download datasheet (18Mb)
Lattice Semiconductor
sysCLOCK GPLL Timing
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. Relative to CLKOP.
5. Value of external capacitor: 5.6 nF ±20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin.
6. f
IN
OUT
OUT2
VCO
PFD
DT
PH
OPJIT
SK
W
LOCK
PA
IPJIT
FBKDLY
HI
LO
RST
Parameter
4
OUT
2
1
(max) = f
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP,
CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width (RESETM/RESETK)
Reset Signal Pulse Width (CNTRST)
IN
* 10 for f
IN
LOCK
< 5MHz.
Description
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
N/M = integer
90% to 90%
10% to 10%
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Default duty cycle selected
f
50 f
f
At 90% or 10%
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
OUT
OUT
3-35
100 MHz
< 50 MHz
OUT
< 100 MHz
Conditions
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
5, 6
5
5
5, 6
5
5
3
0.156
0.039
Min.
640
500
0.5
0.5
20
20
20
45
85
15
20
—
—
—
—
—
—
—
—
—
2
5
2
1
Typ.
130
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±0.05
0.025
Max.
1280
±125
±250
±200
0.04
420
420
420
210
420
150
500
360
50
25
50
55
10
—
—
—
—
—
—
Units
UIPP
UIPP
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
µs
µs
ns
ns
µs
UI
ps
ns
ps
ps
ns
ns
ns
%
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