LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 673
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LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 673 of 769
- Download datasheet (18Mb)
LatticeECP2/M
Lattice Semiconductor
sysDSP Usage Guide
MAC Module
The MAC Module configures multiply accumulate elements to be packed into the primitive MULT18X18MACB. The
Basic mode, shown in Figure 14-4, consists of an optional one clock, one clock enable and one reset tied to all reg-
isters. Because of the accumulator, the output register is automatically enabled. Multiple sysDSP Blocks can be
spanned to accommodate large multiplications. The accumulator of the sysDSP block is 52 bits deep and addi-
tional LUTs can be used if a larger accumulation is required. If sysDSP blocks are spanned, additional LUT logic
may be required. Select Area/Speed to determine the LUT implementation. The input data format can be selected
as Parallel, Shift or Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The Shift format
enables a sample/shift register. The Accumsload loads the accumulator with the value from the LD port. This is
required to initialize and load the first value of the accumulation. The Advanced mode, shown in Figure 14-5, allows
finer control over the registers. In the advanced mode, users can control each register with independent clocks,
clock enables and resets. MAC inputs can be from 2 to 72 bits.
Figure 14-4. MAC Mode Basic Set-up
14-4
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