LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 502

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

March 2011
Introduction
The LatticeECP2™ and LatticeECP2M™ sysIO™ buffers give the designer the ability to easily interface with other
devices using advanced system I/O standards. This technical note describes the sysIO standards available and
how they can be implemented using Lattice’s ispLEVER
sysIO Buffer Overview
LatticeECP2/M sysIO interface contains multiple Programmable I/O Cells (PIC) blocks. Each PIC contains two Pro-
grammable I/Os (PIO), PIOA and PIOB, connected to their respective sysIO Buffers. Two adjacent PIOs can be
joined to provide a differential I/O pair (labeled as “T” and “C”).
Each Programmable I/O (PIO) includes a sysIO Buffer and I/O Logic (IOLOGIC). The LatticeECP2/M sysIO buffers
supports a variety of single-ended and differential signaling standards. The sysIO buffer also supports the DQS
strobe signal that is required for interfacing with the DDR memory. One of every 16/18 PIOs in the LatticeECP2/M
contains a delay element to facilitate the generation of DQS signals. The DQS signal from the bus is used to strobe
the DDR data from the memory into input register blocks. For more information on the architecture of the sysIO buf-
fer please refer to the
The IOLOGIC includes input, output and tristate registers that implement both single data rate (SDR) and double
data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines
and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals
and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR
memory interface support are discussed in more detail in TN1105,
Supported sysIO Standards
The LatticeECP2/M sysIO buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into internally ratioed standard such as LVCMOS, LVTTL and PCI; and externally refer-
enced standards such as HSTL and SSTL. The buffers support the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V
standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength,
bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch). Other single-ended standards supported
include SSTL and HSTL. Differential standards supported include LVDS, RSDS, BLVDS, LVPECL, differential
SSTL and differential HSTL. Tables 1 and 2 list the sysIO standards supported in LatticeECP2/M devices.
Table 9-1. Supported Input Standards
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
Single Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI 33
HSTL18 Class I, II
HSTL15 Class I
SSTL3 Class I, II
Input Standard
LatticeECP2/M Family Data
Sheet.
V
REF
0.75
9-1
0.9
1.5
®
—
—
—
—
—
—
—
(Nom.)
design software.
LatticeECP2/M High-Speed I/O
LatticeECP2/M sysIO
V
Usage Guide
CCIO
Technical Note TN1102
1.8
1.5
3.3
1
—
—
—
—
—
—
—
(Nom.)
Interface.
tn1102_01.9