LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 450

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Case I_a: 8/10bit, EB and DS FIFOs NOT Bypassed
Figure 8-33. 8b10b, EB and DS FIFOs NOT Bypassed
1. The Up Sample FIFO is acting as a Phase Shift FIFO only in this case.
2. The Down Sample FIFO is acting as a Phase Shift FIFO only in this case.
3. The quad level full rate clock from the Tx PLL (ff_tx_f_clk) has direct access to the FPGA Center Clock
TX
RX
AUX
Mux. This is a relatively higher performance path. A Global Clock Tree out of the Center Clock Mux is used
to clock the user’s interface logic in the FPGA. Some leaf nodes of the clock tree are connected to the
FPGA Transmit Input clock (ff_txi_clki), the Elastic Buffer FIFO Read Clock per Channel (ff_ebrd_clki) via
CIB Clk input and the FPGA Receive Input clock (ff_rxi_clki). This case is probably the most common sin-
gle channel use case.
REFCLK
TX PLL
8:1/10:1
SER
TX_CLK
CDR
/2
/4
Recovered Clock (rx_clki)
DEC
Encoder
8b10b
Elastic
Buffer
BYPASS
8-45
LatticeECP2M SERDES/PCS Usage Guide
Sample
Sample
Down
FIFO
FIFO
Up
PCS
/4
/2
ff_rxqtrclk_ch0
ff_rxhalfclk_ch0
ff_rxfullclk_ch0
ff_rxiclk_ch0
ff_ebrd_clk_0
ff_txqtrclk
ff_txhalfclk
ff_txfullclk
ff_txdata_ch0
ff_txiclk_ch0
ff_rxdata_ch0
FPGA
FPGA
Clock
Clock Tree
Tree
Global