LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 6

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
LatticeECP2/M sysIO Usage Guide
SERDES/PCS Reset........................................................................................................................................ 8-62
Power Supply Sequencing Requirements........................................................................................................ 8-64
References....................................................................................................................................................... 8-64
Technical Support Assistance.......................................................................................................................... 8-64
Revision History ............................................................................................................................................... 8-65
Appendix A. Memory Map................................................................................................................................ 8-66
Appendix B. 8b10b Symbol Codes .................................................................................................................. 8-87
Appendix C. Attribute Cross-Reference Table ................................................................................................. 8-88
Appendix D. Protocol Specific SERDES Setup Options .................................................................................. 8-93
Appendix E. Lattice Diamond Usage Overview ............................................................................................... 8-94
Introduction ........................................................................................................................................................ 9-1
sysIO Buffer Overview ....................................................................................................................................... 9-1
Supported sysIO Standards ............................................................................................................................... 9-1
sysIO Banking Scheme...................................................................................................................................... 9-3
LVCMOS Buffer Configurations ......................................................................................................................... 9-6
Simulation of the SERDES/PCS ............................................................................................................. 8-56
Reset Usage in Simulation...................................................................................................................... 8-57
16/20-bit Word Alignment........................................................................................................................ 8-57
Switching Between 10XH, 10X and 20X Reference Clock Multiplier Modes Using SCI ......................... 8-58
Switching Between 20X to 20XH or 10X to 10XH Mode in 16-Bit Interface............................................ 8-58
Off-Chip AC Coupling.............................................................................................................................. 8-58
Unused Quad/Channel and Power Supply ............................................................................................. 8-59
Reset and Power-Down Control.............................................................................................................. 8-59
Power-Down Controls Description .......................................................................................................... 8-61
Reset Sequence and Reset State Diagram ............................................................................................ 8-62
Lock Status Signals Definitions............................................................................................................... 8-62
Configuration Register Definition ............................................................................................................ 8-66
Per Quad Register Overview .................................................................................................................. 8-67
Per Quad PCS Control Register Details ................................................................................................. 8-68
Per Quad SERDES Control Register Details .......................................................................................... 8-71
Per Quad Reset and Clock Control Register Details .............................................................................. 8-73
Per Quad PCS Status Register Details................................................................................................... 8-74
Per Quad SERDES Status Register Details ........................................................................................... 8-76
Per Channel Register Overview.............................................................................................................. 8-77
Per Channel SERDES Control Register Details ..................................................................................... 8-80
Per Channel PCS Status Register Details .............................................................................................. 8-83
Per Channel SERDES Status Register Details....................................................................................... 8-84
Converting an ispLEVER Project to Lattice Diamond ............................................................................. 8-94
Importing an ispLEVER Design Project .................................................................................................. 8-94
Adjusting PCS Modules .......................................................................................................................... 8-94
Regenerate PCS Modules ...................................................................................................................... 8-94
Using IPexpress with Lattice Diamond.................................................................................................... 8-95
Creating a New Simulation Project Using Simulation Wizard ................................................................. 8-96
V
V
V
Input Reference Voltage (V
V
Mixed Voltage Support in a Bank.............................................................................................................. 9-4
sysIO Standards Supported by Bank ........................................................................................................ 9-5
Bus Maintenance Circuit ........................................................................................................................... 9-6
Programmable Drive ................................................................................................................................. 9-6
Programmable Slew Rate ......................................................................................................................... 9-6
CCIO
CCAUX
CCJ
REF1
(1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 9-4
(1.2V/1.5V/1.8V/2.5V/3.3V) ............................................................................................................ 9-4
for DDR Memory Interface ............................................................................................................. 9-4
(3.3V) ........................................................................................................................................... 9-4
REF1,
V
REF2
)................................................................................................... 9-4
5
LatticeECP2/M Family Handbook
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