LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 543

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Figure 10-18. LatticeECP2/M DLL Block Diagram
Both clock injection delay removal and output phase adjustment use only the clock outputs of the DLL. Time refer-
ence delay and delay match modes use the delay control vector output. Specific examples of these features are
discussed later in this document.
DLL Overview
The LatticeECP2/M DLL is created and configured by IPexpress. The following is a list of port names and descrip-
tions for the DLL. There are two library elements used to implement the DLL: CIDDLLA (Clock Injection Delay), and
TRDDLLA (Time Reference Delay). IPexpress will wrap one of these library elements to create a customized DLL
module based on user selections.
DLL Inputs and Outputs
CLKI Input
The CLKI signal is the reference clock for the DLL. The CLKI input can be sourced from any type of FPGA routing
and pin. The DLL CLKI input has a preferred pin per DLL which provides the lowest latency and best case perfor-
mance.
CLKFB Input
The CLKFB input is available only if the user chooses to use a user clock signal for the feedback or in clock delay
match mode. If internal feedback or CLKOS/CLKOP is used for the feedback, this connection will be made inside
the module. In Clock Injection Delay Removal mode, the DLL will align the input clock phase with the feedback
clock phase by delaying the input clock.
In Clock Injection Delay Match mode, the DLL will calculate the delta between the CLKI and CLKFB signals. This
delay value is then output on the DCNTL vector. The DLL CLKFB input has a preferred pin per DLL which is dis-
cussed later in this document. The preferred pin provides the lowest latency and best case performance.
CLKOP Output
An output of the DLL based on the CLKI rate. The CLKOP output can drive primary and edge clock routing.
CLKOS Output
An output of the PLL based on the CLKI rate which can be divided and/or phase shifted. The CLKOS output can
drive the primary and edge clock routing.
DCNTL[8:0] Output
This output of the DLL is used to delay a signal by a specific amount. The DCNTL[8:0] vector connects to a Slave
Delay Line element. The DLL can then control multiple input delays from a single DLL.
ALUHOLD
UDDCNTL
CLKFB
RSTN
CLKI
D4
D2
PFD
ALU
10-19
DELAY
CHAIN
ADJUST
PHASE
LatticeECP2/M sysCLOCK PLL/DLL
DCNTL
Control
DUTY
DUTY
50
50
Design and Usage Guide
D4
D2
CLKOP
CLKOS
LOCK
DCNTL[8:0]