LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 609

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based
PFU-based Distributed Single Port RAM is created using the 4-input LUT (Look-Up Table) available in the PFU.
These LUTs can be cascaded to create larger Distributed Memory sizes.
Figure 11-39 shows the Distributed Single Port RAM module as generated by IPexpress.
Figure 11-39. Distributed Single Port RAM Module Generated by IPexpress
The generated module makes use 4-input LUT available in the PFU. Additional logic like Clock, Reset is generated
by utilizing the resources available in the PFU.
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn), are not available in the hardware prim-
itive. These are generated by IPexpress when the user wants the to enable the output registers in their IPexpress
configuration.
The various ports and their definitions for the memory are as per Table 11-14. The table lists the corresponding
ports for the module generated by IPexpress and for the primitive.
Table 11-14. PFU-based Distributed Single Port RAM Port Definitions
Ports such as Clock Enable (ClockEn) are not available in the hardware primitive. These are generated by IPex-
press when the user wishes to enable the output registers in the IPexpress configuration.
Users have the option of enabling the output registers for Distributed Single Port RAM (Distributed_SPRAM). Fig-
ures 11-40 and 11-41 show the internal timing waveforms for the Distributed Single Port RAM
(Distributed_SPRAM) with these options.
Generated Module
Port Name in
ClockEn
Address
Reset
Clock
Data
WE
Q
ClockEn
Address
Reset
Clock
Port Name in the
Data
WE
PFU Primitive
DO[1:0]
AD[3:0]
DI[1:0]
WRE
CK
—
—
Distributed Single Port
11-35
PFU based
Memory
Clock Enable
Write Enable
Description
Data Out
Address
Data In
Reset
LatticeECP2/M Memory Usage Guide
Clock
Q
Rising Clock Edge
Active State
Active High
Active High
Active High
—
—
—