LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 651
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 651 of 769
- Download datasheet (18Mb)
Lattice Semiconductor
Figure 12-40. ODDRX2B Waveform
DELAYB
Data going to the DDR registers can be optionally delayed using the Delay block. The Delay block receives 4-bit
delay control. The 4-bit delay can be set using fixed multiplier values or it can be controlled by the user. The
DELAYB block is available for use with the input DDR registers.
The DELAYB block can be configured when generating the DDR input modules in the IPexpress tool of the soft-
ware. The delay can be adjusted in 35ps steps. Users can choose from three types of delay values:
A ( Mux0)
B ( Mux1)
Copy of A
Latch C0
Latch C1
Latch F0
( Mux0)
Reg D0
Reg A0
Reg B0
Reg A1
Reg B1
Reg E0
1. Dynamic – The delay value is controlled by the user logic using the DEL[3:0] input of the DELAYB block.
SCLK
SCLK
ECLK
DB0
DB1
DA0
DA1
Q
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
d1
d0
d3
d2
XX
XX
XX
XX
d1
d2
d3
d0
d1
d0
d1
d5
d7
d4
d6
d3
d3
d2
d2
d3
d0
d1
d0
12-33
d1
d6
d5
d7
d4
d1
d11
d2
d3
d5
d10
d4
d5
d9
d8
d3
d2 d3
d7
d4
d5
d7
d6
d6
d7
d5
d4
d10
d11
d9
d8
d5 d6
d13
d15
d9
d8
d9
d6
d7
d12
d14
d7
d7
d11
High-Speed I/O Interface
d8
d9
d11
d10
d11
d10
d9
d8
d14
d12
d13
d15
d9 d10 d11 d12 d13 d14
d17
d19
d11
d12
d10
d13
d13
d16
d18
d11
LatticeECP2/M
d14
d15
d14
d12
d15
d15
d13
d13
d18
d16
d17
d19
..
..
..
..
d17
d16
d17
d14
d15
d15
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