LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 698

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Configuration Pins
The LatticeECP2/M supports two types of configuration pins, dedicated and dual-purpose. The dedicated pins are
used exclusively for configuration; the dual-purpose pins, when not being used for configuration, are available as
extra I/O pins. If a dual-purpose pin is to be used both for configuration and as a general purpose I/O (GPIO) the
user must adhere to the following:
• The I/O type must remain the same, in other words if the pin is a 3.3V CMOS pin (LVCMOS33) during configura-
• The user must select the correct CONFIG_MODE setting and set the PERSISTENT bit to OFF in order to use
• The user is responsible for insuring that no internal or external logic will interfere with device configuration.
Also, if slave parallel configuration mode is not being used then one or both of the parallel port chip selects (CSN,
CS1N) must be high or tri-state during configuration.
Programmable options control the direction and type of each dual-purpose configuration pin. These options are
controlled via pin preferences in Lattice ispLEVER and Diamond software, or as HDL source file attributes.
The LatticeECP2/M also supports ispJTAG for configuration, transparent read back, and JTAG testing. The follow-
ing sections describe the function of the various sysCONFIG and JTAG pins. Table 15-2 is provided for reference.
Table 15-2. Configuration Pins for the LatticeECP2/M
CFG[2:0]
PROGRAMN
INITN
DONE
CCLK
DI/CSSPI0N
DOUT/CSON
CSN
CS1N
WRITEN
BUSY/SISPI
D[0]/SPIFASTN
D[1:6]
D[7]/SPID0
TDI
TDO
TCK
TMS
1. Weak pull-ups consist of a current source of 30µA to 150µA. The pull-ups for sysCONFIG dedicated and dual-purpose pins track V
2. The sysCONFIG pins on the LatticeECP2M50/M70/M100 are dedicated sysCONFIG pins. The sysCONFIG output pins are actively driven
tion it must remain a 3.3V CMOS pin as a GPIO.
the dual-purpose sysCONFIG pins as GPIO after configuration. In ispLEVER
the Design Planner. If you are using Lattice Diamond™ design software, select Tools > Spreadsheet View and
then select the Global Preferences tab in the Spreadsheet View.
the pull-ups for TDI, TDO, and TMS track V
during normal device operation.
2
2
2
2
2
2
2
2
Pin Name
2
Input, weak pull-up
Input, weak pull-up
Bi-Directional Open Drain, weak pull-up
Bi-Directional Open Drain with weak pull-
up, or Active Drive
Input or Output
Input, weak pull up
Output
Input, weak pull-up
Input, weak pull-up
Input, weak pull-up
Output, tri-state, weak pull-up
Input or Output
Input, weak pull-up
Output, weak pull-up
Input with Hysteresis
Input, weak pull-up
CCJ
.
I/O Type
15-2
LatticeECP2/M sysCONFIG Usage Guide
Dedicated
Dedicated
Dedicated
Dedicated
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dual-Purpose
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Pin Type
®
these preferences can be set in
All
All
All
All
All
Serial, SPI, SPIm
Parallel, Serial, SPI
Parallel
Parallel
Parallel
Serial, SPI, SPIm
Parallel, SPI, SPIm
Parallel
Parallel, SPI, SPIm
JTAG
JTAG
JTAG
JTAG
Mode Used
CCIO8
;