TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 14

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

9. DMA Controller(DMAC)
10. Static Memory Controller
vi
9.1 Function Overview................................................................................................................235
9.2 DMA transfer type.................................................................................................................236
9.3 Block diagram.......................................................................................................................237
9.4 Description of Registers........................................................................................................238
9.5 Special Functions...................................................................................................................258
10.1 Function Overview..............................................................................................................261
10.2 Block diagram.....................................................................................................................261
10.3 Description of Registers......................................................................................................262
10.4 External Bus Cycle .............................................................................................................276
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10
8.4.11
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10
9.4.11
9.4.12
9.4.13
9.4.14
9.4.15
9.4.16
9.4.17
9.5.1
9.5.2
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.3.9
10.3.10
10.3.11
10.3.12
10.3.13
10.3.14
10.4.1
10.4.1.1
10.4.1.2
Port E Setting..................................................................................................................................................................226
Port F Setting...................................................................................................................................................................227
Port G Setting..................................................................................................................................................................228
Port I Setting....................................................................................................................................................................229
Port J Setting...................................................................................................................................................................230
Port L Setting..................................................................................................................................................................231
Port M Setting.................................................................................................................................................................232
DMAC register list..........................................................................................................................................................238
DMACIntStatus (DMAC Interrupt Status Register)......................................................................................................239
DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register)......................................................................240
DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register).........................................................................241
DMACIntErrorStatus (DMAC Interrupt Error Status Register)....................................................................................242
DMACIntErrClr (DMAC Interrupt Error Clear Register).............................................................................................243
DMACRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register)......................................................244
DMACRawIntErrorStatus (DMAC Raw Error Interrupt Status Register)....................................................................245
DMACEnbldChns (DMAC Enabled Channel Register)................................................................................................246
Scatter/gather function.....................................................................................................................................................258
Linked list operation........................................................................................................................................................259
Port N setting.................................................................................................................................................................233
Port P Setting.................................................................................................................................................................234
DMACSoftBReq (DMAC Software Burst Request Register).....................................................................................247
DMACSoftSReq (DMAC Software Single Request Register)....................................................................................249
DMACConfiguration (DMAC Configuration Register)...............................................................................................250
DMACCxSrcAddr (DMAC Channelx Source Address Register)...............................................................................251
DMACCxDestAddr (DMAC Channelx Destination Address Register)......................................................................252
DMACCxLLI (DMAC Channelx Linked List Item Register).....................................................................................253
DMACCxControl (DMAC Channelx Control Register)..............................................................................................254
DMACCxConfiguration (DMAC Channelx Configuration Register)..........................................................................256
SFR List.........................................................................................................................................................................262
SMCMDMODE (Mode Register).................................................................................................................................263
smc_memif_cfg (SMC Memory Interface Configuration Register)............................................................................264
smc_direct_cmd (SMC Direct Command Register).....................................................................................................265
smc_set_cycles (SMC Set Cycles Register).................................................................................................................266
smc_set_opmode (SMC Set Opmode Register)...........................................................................................................267
smc_sram_cycles0_0 (SMC SRAM Cycles Registers 0 <0>).....................................................................................268
smc_sram_cycles0_1 (SMC SRAM Cycles Registers 0 <1>).....................................................................................269
smc_sram_cycles0_2 (SMC SRAM Cycles Registers 0 <2>).....................................................................................270
Multiplex mode..............................................................................................................................................................276
smc_sram_cycles0_3 (SMC SRAM Cycles Registers 0 <3>)...................................................................................271
smc_opmode0_0 (SMC Opmode Registers 0<0>).....................................................................................................272
smc_opmode0_1 (SMC Opmode Registers 0<1>).....................................................................................................273
smc_opmode0_2 (SMC Opmode Registers 0<2>).....................................................................................................274
smc_opmode0_3 (SMC Opmode Registers 0<3>).....................................................................................................275
tRC / tCEOE setting example
tWC / tWP setting example