TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 17

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

13. Synchronous Serial Port (SSP)
14. Serial Bus Interface (I2C/SIO)
13.1 Overview..............................................................................................................................377
13.2 Block Diagram.....................................................................................................................378
13.3 Register................................................................................................................................379
13.4 Overview of SSP.................................................................................................................389
13.5 SSP operation......................................................................................................................393
13.6 Frame Format......................................................................................................................394
14.1 Configuration.......................................................................................................................402
14.2 Register................................................................................................................................403
14.3 I2C Bus Mode Data Format................................................................................................404
14.4 Control Registers in the I2C Bus Mode..............................................................................405
14.5 Control in the I2C Bus Mode..............................................................................................412
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10
13.3.11
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.5.1
13.5.2
13.5.3
13.6.1
13.6.2
13.6.3
14.2.1
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.5.7
14.5.8
12.16.4.1
12.16.4.2
14.5.1.1
14.5.1.2
Register List...................................................................................................................................................................379
SSPCR0(Control register 0)..........................................................................................................................................380
SSPCR1(Control register1)...........................................................................................................................................381
SSPDR(Data register)....................................................................................................................................................382
SSPSR(Status register)..................................................................................................................................................383
SSPCPSR (Clock prescale register)..............................................................................................................................384
SSPIMSC (Interrupt enable/disable register)................................................................................................................385
SSPRIS (Pre-enable interrupt status register)...............................................................................................................386
SSPMIS (Post-enable interrupt status register)............................................................................................................387
Clock prescaler..............................................................................................................................................................389
Transmit FIFO...............................................................................................................................................................389
Receive FIFO.................................................................................................................................................................389
Interrupt generation logic..............................................................................................................................................390
DMA interface...............................................................................................................................................................392
Initial setting for SSP....................................................................................................................................................393
Enabling SSP.................................................................................................................................................................393
Clock ratios....................................................................................................................................................................393
SSI frame format...........................................................................................................................................................395
SPI frame format...........................................................................................................................................................396
Microwire frame format................................................................................................................................................398
Registers for each channel............................................................................................................................................403
SBIxCR0(Control register 0)........................................................................................................................................405
SBIxCR1(Control register 1)........................................................................................................................................406
SBIxCR2(Control register 2)........................................................................................................................................408
SBIxSR (Status Register)..............................................................................................................................................409
SBIxBR0(Serial bus interface baud rate register 0).....................................................................................................410
SBIxDBR (Serial bus interface data buffer register)....................................................................................................410
SBIxI2CAR (I2Cbus address register)..........................................................................................................................411
Serial Clock...................................................................................................................................................................412
Setting the Acknowledgement Mode............................................................................................................................413
Setting the Number of Bits per Transfer......................................................................................................................413
Slave Addressing and Address Recognition Mode......................................................................................................413
Operating mode.............................................................................................................................................................413
Configuring the SBI as a Transmitter or a Receiver....................................................................................................414
Configuring the SBI as a Master or a Slave.................................................................................................................414
Generating Start and Stop Conditions..........................................................................................................................414
SSPICR (Interrupt clear register)................................................................................................................................388
SSPDMACR (DMA control register).........................................................................................................................388
Clock source
Clock Synchronization
Wake-up Function
Protocol
ix