TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 531

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.4.23
31-16
15-8
7-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
counter <TEC>. The value of both counters can be read from the CPU. A write access to the error counters
is only possible in test error mode (The <TSTERR> bit in the CANMCR register is "1"). In the case of a
write to the CANCEC register, the write data to the lower 8 bits <REC> is written also to the higher 8 bits
(TEC).
rect reception of a message, the <REC> is set to a value between 119 and 127. After reaching the "bus off" sta-
tus, the error counters are undefined.
bits on the bus. If the counter reaches the count 128, the module changes automatically to the status error ac-
tive. All internal flags are reset and the error counters will be cleared to "0". The configuration registers keep
the programmed values. The values of the counters are undefined during "bus off" status.
−
TEC[7:0]
REC[7:0]
The CAN controller contains two error counters : the receive error counter <REC> and the transmit error
The CAN error counters count up or down according to the CAN Specification 2.0B.
The <REC> is not increased after exceeding the error passive limit (128).When <REC>=128, after the cor-
If the status "bus off" is reached, the receive error counter is incremented after 11 consecutive recessive
When CAN enters configuration mode, the error counters will be cleared.
Bit Symbol
CANCEC (Error Counter Register)
31
23
15
0
0
0
7
0
-
-
R
R
R/W
R
R/W
Type
30
22
14
0
0
0
6
0
Read : Read as "0".
Write : Write as "0".
8-bit transit error counter (After reset release)
8-bit transit error counter (CANMCR<TSTERR>="1")
8-bit receive error counter (After reset release)
8-bit receive error counter (CANMCR<TSTERR>="1")
-
-
29
21
13
0
0
0
5
0
-
-
Page 505
28
20
12
0
0
0
4
0
-
-
TEC
REC
27
19
11
Function
0
0
0
3
0
-
-
26
18
10
0
0
0
2
0
-
-
25
17
0
0
9
0
1
0
-
-
TMPM363F10FG
24
16
0
0
8
0
0
0
-
-