TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 599

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

18.6.13
31-4
3-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
added to the Done queue. In normal operation, the Host Controller Driver should not need to read this regis-
ter as its content is periodically written to the HCCA.
DH[27:0]
−
The HcDoneHead register contains the physical address of the last completed Transfer Descriptor that was
Bit Symbol
HcDoneHead Register
31
23
15
0
0
0
7
0
R
−
(HCD)
Type
30
22
14
0
0
0
6
0
R/W
−
Type
(HC)
DH
Filed name:Done Head
When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD.
HC then overwrites the content of HcDoneHead with the address of this TD.
This is set to zero whenever HC writes the content of this register to HCCA. It also sets the Write-
backDoneHead of HcInterruptStatus.
Reserved
29
21
13
0
0
0
5
0
Page 573
28
20
12
0
0
0
4
0
DH
DH
DH
27
19
11
0
0
0
3
-
Function
26
18
10
0
0
0
2
-
25
17
0
0
9
0
1
-
TMPM363F10FG
24
16
0
0
8
0
0
-