TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 18

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

15. Consumer Electronics Control (CEC)
x
14.6 Data Transfer Procedure in the I2C Bus ModeI2C............................................................419
14.7 Control register of SIO mode..............................................................................................428
14.8 Control in SIO mode...........................................................................................................434
15.1 Outline.................................................................................................................................441
15.2 Block Diagram.....................................................................................................................442
15.3 Registers..............................................................................................................................443
15.4 Operations............................................................................................................................462
14.5.9
14.5.10
14.5.11
14.5.12
14.5.13
14.5.14
14.5.15
14.5.16
14.6.1
14.6.2
14.6.3
14.6.4
14.6.5
14.7.1
14.7.2
14.7.3
14.7.4
14.7.5
14.7.6
14.8.1
14.8.2
15.1.1
15.1.2
15.1.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.3.6
15.3.7
15.3.8
15.3.9
15.3.10
15.3.11
15.3.12
15.3.13
15.3.14
15.3.15
15.4.1
15.4.2
14.6.2.1
14.6.2.2
14.6.3.1
14.6.3.2
14.8.1.1
14.8.1.2
14.8.2.1
14.8.2.2
14.8.2.3
14.8.2.4
15.4.2.1
15.4.2.2
15.4.2.3
Interrupt Service Request and Release.........................................................................................................................415
Device Initialization......................................................................................................................................................419
Generating the Start Condition and a Slave Address...................................................................................................419
Transferring a Data Word.............................................................................................................................................421
Generating the Stop Condition......................................................................................................................................426
Restart Procedure...........................................................................................................................................................426
SBIxCR0(control register 0).........................................................................................................................................428
SBIxCR1(Control register 1)........................................................................................................................................429
SBIxDBR (Data buffer register)...................................................................................................................................430
SBIxCR2(Control register 2)........................................................................................................................................431
SBIxSR (Status Register)..............................................................................................................................................432
SBIxBR0 (Baud rate register 0)....................................................................................................................................433
Serial Clock...................................................................................................................................................................434
Transfer Modes..............................................................................................................................................................436
Reception.......................................................................................................................................................................441
Transmission..................................................................................................................................................................441
Precautions.....................................................................................................................................................................441
Register List...................................................................................................................................................................443
CECEN (CEC Enable Register)....................................................................................................................................444
CECADD (Logical Address Register ).........................................................................................................................445
CECRESET (Software Reset Register)........................................................................................................................446
CECREN (Receive Enable Register)............................................................................................................................447
CECRBUF (Receive Buffer Register)..........................................................................................................................448
CECRCR1 (Receive Control Register 1)......................................................................................................................449
CECRCR2 (Receive Control Register 2)......................................................................................................................451
CECRCR3 (Receive Control Register 3 )....................................................................................................................453
Sampling clock..............................................................................................................................................................462
Reception.......................................................................................................................................................................462
Arbitration Lost Detection Monitor............................................................................................................................415
Slave Address Match Detection Monitor....................................................................................................................417
General-call Detection Monitor...................................................................................................................................417
Last Received Bit Monitor..........................................................................................................................................417
Data Buffer Register (SBIxDBR)...............................................................................................................................417
Baud Rate Register (SBIxBR0)..................................................................................................................................418
Software Reset.............................................................................................................................................................418
CECTEN (Transmit Enable Register).........................................................................................................................455
CECTBUF (Transmit Buffer Register).......................................................................................................................456
CECTCR (Transmit Control Register).......................................................................................................................457
CECRSTAT (Receive Interrupt Status Register).......................................................................................................459
CECTSTAT (Transmit Interrupt Status Register)......................................................................................................460
CECFSSEL(CEC Sampling Clock Select Register)...................................................................................................461
Master mode
Slave mode
Master mode (<MST> = "1")
Slave mode (<MST> = "0")
Clock source
Shift Edge
8-bit transmit mode
8-bit receive mode
8-bit transmit/receive mode
Data retention time of the last bit at the end of transmission
Basic Operation
Preconfiguration
Enabling Reception