TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 770

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

27.6
AC Electrical Characteristics
27.6.5
SPCLK period (Master)
SPCLK period (Slave)
SPCLK rise up time
SPCLK fall down time
Master mode : SPCLK low-level pulse width
Master mode : SPCLK high-level pulse width
Slave mode : SPCLK low-level pulse width
Slave mode : SPCLK high-level pulse width
Master mode :
SPCLK rise / fall → output valid
Master mode :
SPCLK rise / fall → output data hold
Master mode :
SPCLK rise / fall → input data valid delay time
Master mode :
SPCLK rise / fall → input data hold
Master mode :
SPFSS valid → SPCLK rise / fall
Slave mode :
SPCLK rise / fall → output data valid delay time
Slave mode :
SPCLK rise / fall → output data hold
Slave mode :
SPCLK rise / fall → input data valid delay time
Slave mode :
SPCLK rise / fall → input data hold
Slave mode :
SPFSS valid → SPCLK rise / fall
"T" is 1/2 cycles of an internal bus frequency (fsys) in the Equation of the table.
AC measurement condition
SSP Controller (SSP)
Note:The "Equation" column in the table shows the specifications under the conditions DVDD3 2.7
Note:Baud rate clock is set under below condition
・ Output level : High = 0.8 x DVDD3, Low = 0.2 x DVDD3
・ Input level : Refer low-level input voltage and high-level input voltage in DC Electrical Characteris-
・ Load capacitance : CL = 30pF
tics.
to 3.6 V.
Parameter
Page 744
Symbol
t
t
t
t
t
t
t
t
t
t
t
ODSM
ODHM
t
t
t
OFSM
ODSS
ODHS
IDHM
OFSS
WLM
WHM
WHS
IDSM
IDSS
IDHS
WLS
T
T
t
t
m
r
f
s
However more than
(m)T / 2 − 10.0
(m)T / 2 − 10.0
(m)T / 2 − 10.0
(n)T / 2 − 10.0
(n)T / 2 − 10.0
(n)T / 2 + (2T)
(m)T − 10.0
(3T) + 10.0
(n)T − 15.0
50 ns
(m)T
(n)T
15.0
5.00
0.00
Min
−
−
−
−
Equation
(m)T + 10.0
(3T) + 22.0
Max
10.0
10.0
15.0
−
−
−
−
−
−
−
−
−
−
−
−
−
52.5 − 72.5
(16MHz)
64 MHz
(8MHz)
n = 12
fsys =
m = 4
TMPM363F10FG
187.5
172.5
62.5
10.0
10.0
21.3
21.3
83.8
83.8
15.0
21.3
15.0
5.00
68.9
0.00
56.9
125
Unit
ns