TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 406

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

13.3
Register
13.3.2
31-16
15-8
7
6
5-4
3-0
After Reset
After Reset
After Reset
After Reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
−
SCR[7:0]
SPH
SPO
FRF[1:0]
DSS[3:0]
Bit Symbol
SSPCR0(Control register 0)
Undefined
Undefined
SPH
31
23
15
0
7
0
-
-
W
R/W
R/W
R/W
R/W
R/W
Type
Undefined
Undefined
SPO
30
22
14
0
6
0
-
-
Write as "0".
For serial clock rate setting.
Parameter : 0x00 to 0xFF.
Bits to generate the SSP transmit bit rate and receive bit rate.
This bit rate can be obtained by the following equation.
Bit rate = f
<CPSDVSR> is an even number between 2 to 254, which is programmed by the SSPCPSR register, and
<SCR> takes a value between 0 to 255.
SPCLK phase:
0 : Captures data at the 1st clock edge.
1 : Captures data at the 2nd clock edge.
This is applicable to Motorola SPI frame format only. Refer to Section "Motorola SPI frame format"
SPCLK polarity:
0:SPCLK is in Low state.
1:SPCLK is in High state.
This is applicable to Motorola SPI frame format only. Refer to Section "Motorola SPI frame format"
Frame format:
Data size select:
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
00: SPI frame format
01: SSI serial frame format
10: Microwire frame format
11: Reserved, undefined operation
sys
Undefined
Undefined
Reserved, undefined op-
eration
Reserved, undefined op-
eration
Reserved, undefined op-
eration
4 bits data
5 bits data
6 bits data
7 bits data
8 bits data
/ (<CPSDVSR> × (1+ <SCR>))
29
21
13
0
5
0
-
-
FRF
Page 380
Undefined
Undefined
28
20
12
0
4
0
-
-
SCR
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
Undefined
Undefined
Description
27
19
11
9 bits data
10 bits data
11 bits data
12 bits data
13 bits data
14 bits data
15 bits data
16 bits data
0
3
0
-
-
Undefined
Undefined
26
18
10
0
2
0
-
-
DSS
Undefined
Undefined
25
17
9
0
1
0
-
-
TMPM363F10FG
Undefined
Undefined
24
16
8
0
0
0
-
-