TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 576

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

17.4
Operation Description
17.4.1.7
17.4.1.8
Remote control signal
waveform
Reversed remote control
signal waveform
(input from RXIN)
ly has low width.
To enable the signal, it must be sent after being reversed by setting the RMCRCR4 <RMCPO> bit to "1".
>=0y0000 _ 0000,<RMCLCMAX[7:0]>><RMCLCMIN[7:0]>.
<RMCDATL[6:0]>.
RMCRCR2, and configure the low-pulse width detection with <RMCLL[7:0]>.
ceiving the last bit, receiving data is completed.
A signal in the phase method has three waveform patterns (see the figure shown below).
ta "0" or "1". On completion of reception, received data "0" and "1" are stored in the RMCRBUF1,
RMCRBUF 2 and RMCRBUF3.
The figure shown below illustrates a remote control signal that starts with a leader of which waveform on-
This signal starts with a leader that only has low width and a data bit cycle starts from the rising edge.
This is because RMC is configured to detect a data bit cycle from the falling edge
To detect a leader, configure only low-pulse width of the leader with the <RMCLLMAX[7ÅF0]
In this case, the value of <RMCLLMIN[7:0]> is set as "don't care".
To detect whether data "0" or data "1", configure the threshold of 0/1 detection with the RMCRCR3
The maximum data bit cycle is configured with the <RMCDMAX[7:0]> of the RMCRCR2.
To complete data reception, configure the maximum data bit cycle with <RMCDMAX[7:0]> of the
After detecting the maximum data bit cycle and confirming the low-pulse with which is specified after re-
The RMC generates an interrupt and waits for the next leader.
RMC is capable of receiving a remote control signal in a phase method of which signal cycle is fixed.
By setting two thresholds a remote control signal pattern is determined. RMC converts the signal into da-
A Leader only with Low Width
Receiving a Remote Control Signal in a Phase Method
Witing for a leader
Leader
Leader detection interrupt
Page 550
Detecting maximum data bit cycle completes reception.
Final bit
Low period
Low width detection interrupt
Waiting for a next leader
TMPM363F10FG