TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 283
TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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4-1
0
Bit
SrcPeripheral
[3:0]
E
Note 1: When you selected Memory-to-Memory, hardware start triggered by DMA is not supported. Transfer is star-
Note 2: Refer to Table 9-3 for the peripheral number of DMA request.
Bit Symbol
ted by writing <E>= 1.
R/W
R/W
Type
Transfer source peripheral (Note2)
0000Å`1111
This is a DMA request peripheral number in binary.
This setting will be ignored if memory is specified as the transfer source.
Channel enable
0 : Disable
1 : Enable
This bit is used to enable or disable the channel. (When memory to memory transfer is set, this bit oper-
ates as a transfer start bit.)
When total number of transfers of DMACCxControl register is complete (the value becomes 0), the corre-
sponding channel is automatically cleared.
If the channel is disabled during a transfer, the data in the channel of FIFO will be lost. To re-start the trans-
fer, all channels must be initialized to reset.
To stop DMA transfer temporarily, use the <Halt> bit to disable DMA requests. Poll the <Active> bit until it be-
comes 0, and then clear the <E> bit to disable the channel.
Page 257
Description
TMPM363F10FG
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