TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 515

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TMPM363F10FG

Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM363F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM363F10FG
Manufacturer:
Toshiba
Quantity:
10 000
16.4.9
31
30-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
When the mailbox interrupt is enabled by setting the corresponding <MBIMx> bit in the mailbox interrupt
mask register CANMBIM to "1", the <MBTIFx> bit of the mailbox transmit interrupt flag register CAN-
MBTIF is set to "1" and the CAN transmit completion interrupt INTCANTX occurs.
write of "0" to the <TAx> bit or the CANTRS<TRSx> bit from the CPU is invalid.
TA30 to TA0
The CANTA<TAx> bit is set to "1" when a message in mailbox x has been successfully transmitted.
A write of "1" to the <TAx> bit or the CANTRS<TRSx> bit from the CPU can clear the <TAx> bit. A
Bit Symbol
CANTA (Transmission Acknowledge Register)
Note:Mailbox 31 is receive-only mailbox.
TA23
TA15
TA7
31
23
15
0
0
0
7
0
-
R
R/W
Type
TA30
TA22
TA14
TA6
30
22
14
0
0
0
6
0
Read : Read as "0".
Write : Write as "0".
Transmission acknowledge (Each bit corresponds with mailboxes 30 to 0)
When the message in mailbox x has been successfully transmitted, the <TAx> bit is set to "1".
The <TAx> bit can be cleared by a write of "1" from the CPU to the <TAx> bit or the TRS<TRSx> bit.
TA29
TA21
TA13
TA5
29
21
13
0
0
0
5
0
Page 489
TA28
TA20
TA12
TA4
28
20
12
0
0
0
4
0
TA27
TA19
TA11
TA3
27
19
11
Function
0
0
0
3
0
TA26
TA18
TA10
TA2
26
18
10
0
0
0
2
0
TA25
TA17
TA9
TA1
25
17
0
0
9
0
1
0
TMPM363F10FG
TA24
TA16
TA8
TA0
24
16
0
0
8
0
0
0

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