TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 609

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

18.6.22
31-21
20
19
18
17
16
15-10
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
streamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower
word is used to reflect the port status, whereas the upper word reflects the status change bits. Some status
bits are implemented with special write behavior (see below). If a transaction (token through handshake) is
in progress when a write to change port status occurs, the resulting port status change must be postponed un-
til the transaction is complete. Reserved bits should always be written "0".
−
PRSC
OCIC
PSSC
PESC
CSC
−
The HcRhPortStatus1 register is used to control and report port events on a per-port basis. NumberDown-
Bit Symbol
HcRhPortStatus1 Register
31
23
15
7
-
-
-
-
−
R/W
R/W
R/W
R/W
R/W
−
(HCD)
Type
30
22
14
6
−
R/W
R/W
R/W
R/W
R/W
−
-
-
-
-
Type
(HC)
Reserved
Filed name:Port Reset Status Change
This bit is set at the end of the 10 ms port reset signal.
The HCD writes a "1" to clear this bit. Writing a "0" has no effect.
0: port reset is not complete.
1: port reset is complete.
Filed name:Port Over Current Indicator Change
This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set
when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a "1" to clear this bit.
Writing a "0" has no effect.
0: No change in PortOverCurrentIndicator
1: PortOverCurrentIndicator has changed.
Filed name:Port Suspend Status Change
This bit is set when the full resume sequence has been completed. This sequence includes the
20 s resume pulse, LS EOP, and 3 ms resynchronization delay. The HCD writes a "1" to clear
this bit. Writing a "0" has no effect. This bit is also cleared when ResetStatusChange is set.
0: Resume is not complete.
1: Resume is complete.
Filed name:Port Enable Status Change
This bit is set when hardware events cause the PortEnableStatus bit to be cleared. Changes from
HCD writing do not set this bit. The HCD writes a "1" to clear this bit. Writing a "0" has no effect.
0: No change in PortEnableStatus.
1: Change in PortEnableStatus.
Filed name:Connect Status Change
This bit is set whenever a connect or disconnect event occurs. The HCD writes a "1" to clear this
bit. Writing a "0" has no effect. If CurrentConnectStatus is cleared when a SetPortReset, SetPortEn-
able, or SetPortSuspend write occurs, this bit is set to force the driver to re-evaluate the connec-
tion status since these writes should not occur if the port is disconnected.
0: No change in CurrentConnectStatus.
1: Change in CurrentConnectStatus
(Note)
If the DeviceRemovable[NDP] bit is set, this bit informs to set only a Root Hub reset while the de-
vice is is attached to the system.
Reserved
29
21
13
5
-
-
-
-
Page 583
PRSC
PRS
28
20
12
0
4
0
-
-
OCIC
POCI
27
19
11
0
3
0
-
-
Function
PSSC
PSS
26
18
10
0
2
0
-
-
Undefined
PESC
LSDA
PES
25
17
0
9
1
0
-
TMPM363F10FG
CSC
CCS
PPS
24
16
0
8
0
0
0
-