TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 583

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

18.6
to the memory space. The bus bridge logic for connecting with the CPU also includes control registers.
Note 1: The Open HCI Specification Release 1.0a specifies the FrameRemaining (FR) and FrameRemainingToggle
Note 2: The explanation of "18.6.1 HcRevision Register" to "18.6.23 HcBCR0 Register" are references. About the explan-
The USBHC contains a set of control registers compliant with the Open HCI Specification which are mapped in-
These registers are directly accessible from the CPU via a 32-bit bus.
Register
Hc Revision Register
Hc Control Register
Hc Command Status Register
Hc Interrupt Status Register
Hc Interrupt Enable Register
Hc Interrupt Disable Register
Hc Host Controller Communication Area Register
Hc Period Current Endpoint Descriptor Register
Hc Control Head Endpoint Descriptor Register
Hc Control Current Endpoint Descriptor Register
Hc Bulk Head Endpoint Descriptor Register
Hc Bulk Current Endpoint Descriptor Register
Hc Done Head Register
Hc Frame Interval Register
Hc Frame Remaining Register
Hc Frame Number Register
Hc Period Start Register
Hc Low Speed Threshold Register
Hc Root hub Descriptor A Register
Hc Root hub Descriptor B Register
Hc Root hub Status Register
Hc Root hub Port Status Register
Hc BCR0 Resister
(FRT) bits in the HcFmRemaining register and the FramNumber (FN) bit in the HcFmNumber register as read-on-
for debug purposes. If the HCD writes to these registers, undefined results will occur. These bits must not be
written by the HCD.
ation based on OHCI, refer to "Open HCI Specification Release 1.0a" specification.
ly to the Host Control Driver (HDC). However, the USBHC allows write accesses to these registers by the HCD
Register name
Page 557
HcControlCurrentED
HcPeriodCurrentED
HcCommandStatus
HcInterruptDisable
HcControlHeadED
HcInterruptEnable
HcBulkCurrentED
HcInterruptStatus
HcRhDescriptorA
HcRhDescripterB
HcRhPortStatus1
HcFmRemaining
HcBulkHeadED
HcLSThreshold
HcPeriodStart
HcFmNumber
HcDoneHead
HcFmInterval
HcRhStatus
HcRevision
HcControl
HcHCCA
HcBCR0
Base Address = 0x4000_3000
Address(Base+)
0x000C
0x001C
0x002C
0x003C
0x004C
0x0000
0x0004
0x0008
0x0010
0x0014
0x0018
0x0020
0x0024
0x0028
0x0030
0x0034
0x0038
0x0040
0x0044
0x0048
0x0050
0x0054
0x0080
TMPM363F10FG